On Tue Jan 20, 2026 at 2:29 PM CET, Jan Beulich wrote:
> On 20.01.2026 14:11, Teddy Astie wrote:
>> Le 20/01/2026 à 10:56, Alejandro Vallejo a écrit :
>>> --- a/xen/arch/x86/hvm/svm/vmcb.c
>>> +++ b/xen/arch/x86/hvm/svm/vmcb.c
>>> @@ -66,6 +66,12 @@ static int construct_vmcb(struct vcpu *v)
>>> GENERAL2_INTERCEPT_XSETBV | GENERAL2_INTERCEPT_ICEBP |
>>> GENERAL2_INTERCEPT_RDPRU;
>>>
>>> + if ( cpu_has_bus_lock_thresh )
>>> + {
>>> + vmcb->_general3_intercepts = GENERAL3_INTERCEPT_BUS_LOCK_THRESH;
>>> + vmcb->bus_lock_thresh = 1; /* trigger immediately */
>>> + }
>>> +
>>> /* Intercept all debug-register writes. */
>>> vmcb->_dr_intercepts = ~0u;
>>>
>>
>> According to APM,
>>
>> INTERCEPT_BUS_LOCK_THRESH does
>> > Intercept bus lock operations when Bus Lock Threshold Counter is 0
>>
>> I assume that when set to 0, we intercept all bus locks, so if set to 1,
>> every 2 bus lock (since we first go from 1 to 0, then at 0 we intercept
>> the next one) ?
Correct
>>
>> I think we want that to be tunable, as intercepting all bus locks may be
>> too extreme we probably want to intercept every few ones instead.
>
> Otoh bus locks (as opposed to cache locks) would better be rare, or else
> perhaps such a guest deserves some extra slowing down?
>
> Jan
I agree with Jan. buslock operations are so rare it's not worth being lenient
about them. They ought to be more expensive than they currently are for the
caller, in fact, so they notice and not do it because there's rarely a rationale
for them to exist at all. I'd be happier if the ISA didn't allow them at all.
Cheers,
Alejandro
