On Wed, Aug 14, 2024 at 7:31 AM Marcus D. Leech <patchvonbr...@gmail.com> wrote:
> On 13/08/2024 15:16, Brajesh wrote: > > > > On Wed, Aug 14, 2024 at 12:14 AM Marcus D. Leech <patchvonbr...@gmail.com> > wrote: > >> On 13/08/2024 14:32, Brajesh wrote: >> >> Thanks Marcus for response. >> >> Yes, you are correct that I am beginner to UHD related issues. Maybe I >> should have pointed in my first posting. Sorry for that. But for design >> implementations on FPGA boards viz Basys 3 etc using AMD/Xilinx tools viz. >> ISE/Vivado/Vitis I am OK. A useful link ( >> https://www.amd.com/content/dam/amd/en/documents/university/vivado-teaching/hdl-design/2015x/Verilog/docs-pdf/Vivado_tutorial.pdf >> ) is shared for confidence building. >> >> Further, I am not communication field expert either. I am >> building/brushing basics of communications fundamentals using GNU Radio. I >> have already gone though the link you shared before posting to forum. Now, >> I am inferring (confirming) that to modify N210 FPGA one need to follow the >> link you shared not standard AMD/Xilinx tool kit flow. Kindly note, due to >> my previous FPGA experience, I was trying to look for a way out to >> implement Ettus Research GitHub code using standalone process of AMD/Xilinx >> tool flow which was genesis of putting forward issue ( i ) in my previous >> thread. Not to mention I have no help, on the subject matter, around >> either. Now, I can ascertain that one need not to follow standalone flow of >> AMD/Xilinx tool kit for mentioned cause. This settles first issue. >> >> *Summary:-* >> Modifying N210 FPGA is a two step process, >> >> i) Generate bit file ( >> https://files.ettus.com/manual/md_usrp2_build_instructions.html ) >> ii) Use iMPACT tool to load firmware called "bit" file ( output of step >> (i)) on N210 FPGA using JTAG cable >> >> >> Experts confirmation is need of hour though. >> >> You CAN jtag images into the FPGA, but the usual route is to use the >> uhd_image_loader tool to do this, from the appropriate >> generated artifacts. Since new releases of UHD often include new FPGA >> code, "uhd_image_loader" allows end-users to >> load new "factory" images into their devices without needing Xilinx >> tooling. >> > > Thanks Marcus, for clarifying. > >> >> ---------------------------------------------- >> >> However, following doubt still remains, >> >> i. How to customise the data rate of N210, if possible, of design >> available at the GitHub link ( >> https://github.com/EttusResearch/uhd/tree/master/fpga/usrp2/top ). I >> wish, if possible, to make the data rate as 1-bit, 2-bit, 4- bit, 8-bit, >> 16-bit, 32-bit and 64-bit. For N210's FPGA specifications, I referred >> section "comparative feature list" available at following link, >> >> https://files.ettus.com/manual/page_usrp2.html >> >> There is no "structured walk-through" of the FPGA code avalable. The >> existing code for the N210 family USRPs includes support >> for 16-bit and 8-bit samples "on the wire". If it were my problem, >> that's where I'd start. When you say "data rate", I assume >> that you mean "data format on the wire". I'm guessing that you want to >> move samples at a higher rate "over the wire" >> than the 16 and 8 bit formats support. Since the ADCs are only 14-bit >> on the N210, there's little point in carrying samples >> wider than that over the wire. >> >> I would *not* go down that road without having a very thorough knowledge >> of how the standard FPGA data-flow works. As I said >> there is no "tell me how all this works" document, other than the >> Verilog source code. The way that *most* users use these >> devices is with the standard FPGA images, and the host-side UHD >> library. Ettus/NI/Emerson don't provide a lot of hand-holding >> documentation in this regard. >> > > I tried to get a complete picture of the schematic from Ettus Research ( > https://files.ettus.com/schematics/usrp2/usrp2.pdf ) but it is not giving > complete information. Hene I am a bit not clear. For standard FPGA data > flow, I have experience to move on unlike this issue. > > Not sure why you'd be using the USRP2 schematic if you have an N210. The > N210 schematics are here: > > https://files.ettus.com/schematics/n200/ > > The N210/N200 are basically the same device, with the N210 having a larger > FPGA. > > Note that the USRP2 has been EOL for MANY years. The N210 was originally > released back in 2011, and has had no major hardware > updates since then, and the FPGA image hasn't been updated a whole lot > since then. > Thanks, Marcus, for clarifying. > > > > Kind request to Ettus Research associates:- > Give me some pointers here. > > > https://kb.ettus.com/Knowledge_Base > > That's a good "top level" starting point. > Well, I took a chance by writing to supp...@ettus.com ( https://kb.ettus.com/Email ) but got no response as it was expected / already mentioned over the link. > > Request to community people :- > > If possible, kindly share Ettus Research fellow's email so that I can > directly post my query to them. This request is to keep everyone's interest > intact. > > I *AM* (for purposes of this forum) an Ettus/NI/Emerson "fellow". But i > work very part-time. > That's great. If possible, request your time for interactive session. This request is to understand codebase ( https://github.com/EttusResearch/fpga/commit/78eab419fdcdc18f4da8fd33f267af6c4d0494f6 ) and get starting point to start for data rate modifications. > > I'm not sure what you're looking for apart from what you've already found, > and I've already pointed you to. The FPGA source-code > is freely available. There are documents that describe the work-flow > for making custom mods to the N2xx FPGA images. > The FPGA "architecture" is common between (obsolete) USRP2 and N2xx > hardware. The follow-on architecture is referred > to in the FPGA codebase as "usrp3", but that's just the naming of the > FPGA architecture. > > Like I have said previously, there is no "structured walk-through" > document that describes, in a high-level way, the architecture > of the FPGA codebase. The codebase is the document. The same is > basically true for the host-side UHD library. The architecture > changes often-enough that by the time a "structured walk-through" > document could be considered "complete", the architecture > underneath it, at least the details, would have changed. Such is the > nature of an evolving code-base. > > Now, for the "usrp2" FPGA architecture, THAT codebase has been relatively > static for many years. But a goodly chunk of it > was written by people who have long-since departed the company. > Occasional maintenance is done on it, but for the > most part, it has been the same for many years. Again, though, the > codebase IS the documentation. > > Thanks again for shared details.
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