On 13/08/2024 08:39, Brajesh wrote:
Hello all,
I am Brajesh and working on Ettus Research N210 FPGA board
modifications. While doing so, I am facing some issues which are
listed below,
i. How to implement Verilog code ( available at following GitHub
link ) on N210's ( Ettus Research ) FPGA ,
https://github.com/EttusResearch/uhd/tree/master/fpga/usrp2/top/N2x0
ii. How to customize the data rate of the above GitHub link. I am
trying to make the data rate ( via connector to PC/Laptop ) as
1-bit, 2-bit, 4- bit, 8-bit, 16-bit(default), 32-bit and 64-bit.
iii. Once N210's FPGA is modified with above modifications, how to
check the correctness of modified FPGA of N210. What I mean here
is, methodologies ( standalone ) to check faithfulness of N210's
FPGA ( modified ) without daughter boards.
For the same, I kindly request your valuable suggestions. If you are
busy enough or not the right person, I kindly request you to direct me
to the exact person.
Warm regards,
Brajesh
This guide might help some:
https://files.ettus.com/manual/md_usrp2_build_instructions.html
But the tone of your questions suggests that you aren't already familiar
with the tools and techniques of FPGA development,
and if so, no amount of casual advice given here can bridge that gap.
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