Thanks Marcus for response. Yes, you are correct that I am beginner to UHD related issues. Maybe I should have pointed in my first posting. Sorry for that. But for design implementations on FPGA boards viz Basys 3 etc using AMD/Xilinx tools viz. ISE/Vivado/Vitis I am OK. A useful link ( https://www.amd.com/content/dam/amd/en/documents/university/vivado-teaching/hdl-design/2015x/Verilog/docs-pdf/Vivado_tutorial.pdf ) is shared for confidence building.
Further, I am not communication field expert either. I am building/brushing basics of communications fundamentals using GNU Radio. I have already gone though the link you shared before posting to forum. Now, I am inferring (confirming) that to modify N210 FPGA one need to follow the link you shared not standard AMD/Xilinx tool kit flow. Kindly note, due to my previous FPGA experience, I was trying to look for a way out to implement Ettus Research GitHub code using standalone process of AMD/Xilinx tool flow which was genesis of putting forward issue ( i ) in my previous thread. Not to mention I have no help, on the subject matter, around either. Now, I can ascertain that one need not to follow standalone flow of AMD/Xilinx tool kit for mentioned cause. This settles first issue. *Summary:-* Modifying N210 FPGA is a two step process, i) Generate bit file ( https://files.ettus.com/manual/md_usrp2_build_instructions.html ) ii) Use iMPACT tool to load firmware called "bit" file ( output of step (i)) on N210 FPGA using JTAG cable Experts confirmation is need of hour though. ---------------------------------------------- However, following doubt still remains, i. How to customise the data rate of N210, if possible, of design available at the GitHub link ( https://github.com/EttusResearch/uhd/tree/master/fpga/usrp2/top ). I wish, if possible, to make the data rate as 1-bit, 2-bit, 4- bit, 8-bit, 16-bit, 32-bit and 64-bit. For N210's FPGA specifications, I referred section "comparative feature list" available at following link, https://files.ettus.com/manual/page_usrp2.html ii. (new) Once the FPGA is modified (step ( i )), how to load/burn the modified image into FPGA board. There are instructions available at above link ( issue ( i )) but I am confused. ------------------------------------------------- Kindly note, I have gone through following link and GitHub repository before posting my first thread and is ready with hardware ( connector purchased ) as well as software need ( ISE12.2, iMPACT and UDH driver installed ) and is able get positive response to ping command given to N210 kit after power-on and connecting via LAN cable. https://files.ettus.com/manual/page_usrp2.html In between, I have gone through bird's view of workshop details available at following link, https://kb.ettus.com/images/4/47/Workshop_GnuRadio_Slides_20190507.pdf, However, beginner's tutorial mentioning chronological steps, for data rate choice/modification ( if possible ), generating bit etc files and burning modified FPGA image targeting specific application with example set, is need of hour. I hope Ettus Research people must be having some tutorials on the pointed thread as part of their training sessions. Thanks. On Tue, Aug 13, 2024 at 7:25 PM Marcus D. Leech <patchvonbr...@gmail.com> wrote: > On 13/08/2024 08:39, Brajesh wrote: > > Hello all, > I am Brajesh and working on Ettus Research N210 FPGA board modifications. > While doing so, I am facing some issues which are listed below, > > i. How to implement Verilog code ( available at following GitHub link ) on > N210's ( Ettus Research ) FPGA , > > https://github.com/EttusResearch/uhd/tree/master/fpga/usrp2/top/N2x0 > > ii. How to customize the data rate of the above GitHub link. I am trying > to make the data rate ( via connector to PC/Laptop ) as 1-bit, 2-bit, 4- > bit, 8-bit, 16-bit(default), 32-bit and 64-bit. > > iii. Once N210's FPGA is modified with above modifications, how to check > the correctness of modified FPGA of N210. What I mean here is, > methodologies ( standalone ) to check faithfulness of N210's FPGA ( > modified ) without daughter boards. > > > For the same, I kindly request your valuable suggestions. If you are busy > enough or not the right person, I kindly request you to direct me to the > exact person. > Warm regards, > Brajesh > > This guide might help some: > > https://files.ettus.com/manual/md_usrp2_build_instructions.html > > But the tone of your questions suggests that you aren't already familiar > with the tools and techniques of FPGA development, > and if so, no amount of casual advice given here can bridge that gap. > > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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