Hello everyone,
I'm currently stuck with creating a custom RFNoC bitfile with
rfnoc_image_builder. I'm building the image for a USRP N310 and the software
I'm using is the following:
- Debian 12
- Python 3.11.2
- UHD 4.3.0.0
- Vivado 2021.1 (installed with the additional patch)
The command I use to build the image is (I created the file
n310_rfnoc_fosphor.yml myself):
rfnoc_image_builder -F ~/uhd/fpga -y ~/core_yml/n310_rfnoc_fosphor.yml -t
N310_XG
After an unsuccessful build, the image builder gets stuck with HLS:
========================================================
BUILDER: Building HLS IP addsub_hls
========================================================
BUILDER: Staging HLS IP in build directory...
Waiting for concurrent IP build to finish... (1800s [Ctrl-C to proceed])
I was wondering if there was a way to skip the concurrent IP build, using
Ctrl-C only causes the entire rfnoc_image_builder to exit unsuccessfully with:
make: *** [Makefile:90: N3X0_IP] Interrupt
Waiting for the timeout after 1800 seconds throws the following error that I do
not understand at all:
source /tools/Xilinx/Vitis_HLS/2021.1/scripts/vitis_hls/hls.tcl -notrace
can't read "zny": no such variable
while executing
"0Nyy-&ur-r$$!$-9-)n$ v t-n q- !$zny-%vz'yn&v! -v s!$zn&v! -zr%%ntr%-n$r-v
-&uv%-svyr-"
(file
"/tools/Xilinx/Vitis_HLS/2021.1/common/scripts/error_message.tcl" line 2)
invoked from within
Additional info: before that, I had to upgrade two IP cores provided by UHD in
Vivado manually because rfnoc_image_builder threw the error:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the
following file is locked:
/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci
I would be happy to hear any help or pointers to how I could solve this problem.
Thank you and regards
Luca Bachmaier
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