Hi Wade,

thank you for your reply. Running `make cleanall` and rebuilding gives me the 
error that I originally fixed by manually upgrading the IPs:

[00:00:08] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'hb47_1to2' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the 
following file is locked: 
/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci
…
WARNING: [IP_Flow 19-2162] IP 'hb47_1to2' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
...
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file 
'/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
ERROR: [Vivado 12-398] No designs are open

Something else I noticed when rebuilding is that I get a whole bunch of 
warnings like the following:

WARNING: [Runs 36-547] Tool Strategy 'Rodin Implementation Defaults' from file 
'/tools/Xilinx/Vivado/2021.1/strategies/RDI13.psg' discarded because strategy 
with same name already parsed from 
'/tools/Xilinx/Vivado/2021.1//strategies/RDI13.psg'

I’m confused by the comparison of the second path with the “//”. Aren’t both 
paths listed here the same? Could this be the mismatch you wrote about in your 
mail? The patch should be installed properly though, when I start the script I 
get the version info “* Vivado v2021.1_AR76780 (64-bit)”.

To add, did you perhaps mean `make clean all` instead of `make cleanall`? These 
two commands give me two different outputs. The latter you suggested just 
returns “Cleaning targets and IP...” whereas the former actually starts up 
Vivado and then throws this error:

WARNING: [Device 21-436] No parts matched 'ERROR: Invalid target format. Must 
be 
<arch>/<device>/<package>/<speedgrade>[/<temperaturegrade>[/<silicon_revision>]]
ERROR: Parsed only 2 tokens'
ERROR: [Coretcl 2-106] Specified part could not be found.
[00:00:06] Current task: Initialization +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure

I will report back on your suggestion of commenting out the line ASAP. I would 
be very happy to hear feedback from you regarding the errors/warnings above in 
the meantime.

Regards
Luca



Von: Wade Fife <wade.f...@ettus.com>
Gesendet: Mittwoch, 5. Juli 2023 06:35
An: Bachmaier, Luca <luca.bachma...@iis.fraunhofer.de>
Cc: usrp-users@lists.ettus.com; Nieland, Michael 
<michael.niel...@iis.fraunhofer.de>
Betreff: Re: [USRP-users] RFNoC Image Builder: two problems with Vitis HLS

Hi Luca,

Can you try going into the uhd/fpga/usrp3/top/n3xx/ and running `make cleanall` 
and running the build again? You should not have had to manually upgrade IP 
unless there was some kind of mismatch somewhere. Perhaps you tried building 
first without the patch but didn't clean out the old IP that was generated? A 
version mismatch might explain the HLS error you're getting. If the HLS IP 
continues to give you problems, you could try commenting out this line.

https://github.com/EttusResearch/uhddev/blob/UHD-4.3/fpga/usrp3/lib/hls/Makefile.inc#L7

Wade

On Tue, Jul 4, 2023 at 5:50 AM Bachmaier, Luca 
<luca.bachma...@iis.fraunhofer.de<mailto:luca.bachma...@iis.fraunhofer.de>> 
wrote:
Hello everyone,

I'm currently stuck with creating a custom RFNoC bitfile with 
rfnoc_image_builder. I'm building the image for a USRP N310 and the software 
I'm using is the following:
     - Debian 12
     - Python 3.11.2
     - UHD 4.3.0.0
     - Vivado 2021.1 (installed with the additional patch)

The command I use to build the image is (I created the file 
n310_rfnoc_fosphor.yml myself):
     rfnoc_image_builder -F ~/uhd/fpga -y ~/core_yml/n310_rfnoc_fosphor.yml -t 
N310_XG


After an unsuccessful build, the image builder gets stuck with HLS:
     ========================================================
     BUILDER: Building HLS IP addsub_hls
     ========================================================
     BUILDER: Staging HLS IP in build directory...
     Waiting for concurrent IP build to finish... (1800s [Ctrl-C to proceed])

I was wondering if there was a way to skip the concurrent IP build, using 
Ctrl-C only causes the entire rfnoc_image_builder to exit unsuccessfully with:
     make: *** [Makefile:90: N3X0_IP] Interrupt


Waiting for the timeout after 1800 seconds throws the following error that I do 
not understand at all:
     source /tools/Xilinx/Vitis_HLS/2021.1/scripts/vitis_hls/hls.tcl -notrace
     can't read "zny": no such variable
          while executing
     "0Nyy-&ur-r$$!$-9-)n$ v t-n q- !$zny-%vz'yn&v! -v s!$zn&v! -zr%%ntr%-n$r-v 
-&uv%-svyr-"
          (file 
"/tools/Xilinx/Vitis_HLS/2021.1/common/scripts/error_message.tcl" line 2)
           invoked from within


Additional info: before that, I had to upgrade two IP cores provided by UHD in 
Vivado manually because rfnoc_image_builder threw the error:
     CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the 
following file is locked:
     
/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci


I would be happy to hear any help or pointers to how I could solve this problem.


Thank you and regards
Luca Bachmaier

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