Hello Wade, if this is an indicator for a version mismatch, am I using the wrong version of UHD? I cloned this branch: https://github.com/EttusResearch/uhd/tree/UHD-4.3 (commit 1f8fd3457 uhd: Prepare branch for 4.3.0.0 release) To make sure that we’re on the same page, I reset my repo clone to this commit and deleted the folders build-ip/ and build-N3X0_IP/. When trying to build I still get the error: CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xci … ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
Detailed “log”: BUILDER: Releasing IP location: /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_fft ======================================================== BUILDER: Building IP axi_hb31 ======================================================== BUILDER: Staging IP in build directory... BUILDER: Reserving IP location: /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31 BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2... BUILDER: Building IP... [00:00:00] Executing command: vivado -mode batch -source /home/fobp/sdr/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_hb31.log -nojournal [00:00:08] Current task: Initialization +++ Current Phase: Starting WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked: CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xci CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xci [00:00:08] Current task: Initialization +++ Current Phase: Finished [00:00:08] Executing Tcl: synth_design -top axi_hb31 -part xc7z100ffg900-2 -mode out_of_context [00:00:08] Starting Synthesis Command WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design. WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked: ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xml' ERROR: [Vivado 12-398] No designs are open [00:00:08] Current task: Synthesis +++ Current Phase: Starting [00:00:08] Current task: Synthesis +++ Current Phase: Finished [00:00:08] Process terminated. Status: Failure ======================================================== Warnings: 138 Critical Warnings: 7 Errors: 8 BUILDER: Releasing IP location: /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31 make[1]: *** [/home/fobp/sdr/uhd/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc:20: LIB_IP_AXI_HB31_TRGT] Error 1 make[1]: Leaving directory '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx' make: *** [Makefile:90: N3X0_IP] Error 2 Other than that, commenting out the line https://github.com/EttusResearch/uhddev/blob/UHD-4.3/fpga/usrp3/lib/hls/Makefile.inc#L7 gave me this error: ERROR: [Vivado 12-3437] This command only supports sub-design files marked for netlist generation. To enable this functionality, set the GENERATE_SYNTH_CHECKPOINT property to true. If the GENERATE_SYNTH_CHECKPOINT property is marked read-only, then select 'Report IP Status' from the 'Tools' menu, or run the 'report_ip_status' Tcl command to see why the sub-design is locked. Best regards Luca Von: Wade Fife <wade.f...@ettus.com> Gesendet: Donnerstag, 13. Juli 2023 09:05 An: Bachmaier, Luca <luca.bachma...@iis.fraunhofer.de> Cc: usrp-users <usrp-users@lists.ettus.com>; Nieland, Michael <michael.niel...@iis.fraunhofer.de> Betreff: Re: [USRP-users] RFNoC Image Builder: two problems with Vitis HLS The errors about locked IP usually means the Vivado version doesn't match. But you say it reports 2021.1_AR76780, which seems correct. Running "make cleanall" (cleanall is one word in this case) should clean out any stale files that may have been generated with the wrong version. Just to be sure, make sure the generated IP folder is deleted before you try a clean build. /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/ You should be able to build all the IP without error. Upgrading the IP shouldn't do anything because it is already the correct version for 2021.1_AR76780. Wade On Wed, Jul 12, 2023, 1:44 AM Bachmaier, Luca <luca.bachma...@iis.fraunhofer.de<mailto:luca.bachma...@iis.fraunhofer.de>> wrote: Hi Wade, thank you for your reply. Running `make cleanall` and rebuilding gives me the error that I originally fixed by manually upgrading the IPs: [00:00:08] Current task: Initialization +++ Current Phase: Starting WARNING: [IP_Flow 19-2162] IP 'hb47_1to2' is locked: CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci … WARNING: [IP_Flow 19-2162] IP 'hb47_1to2' is locked: ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified ... CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml' ERROR: [Vivado 12-398] No designs are open Something else I noticed when rebuilding is that I get a whole bunch of warnings like the following: WARNING: [Runs 36-547] Tool Strategy 'Rodin Implementation Defaults' from file '/tools/Xilinx/Vivado/2021.1/strategies/RDI13.psg' discarded because strategy with same name already parsed from '/tools/Xilinx/Vivado/2021.1//strategies/RDI13.psg' I’m confused by the comparison of the second path with the “//”. Aren’t both paths listed here the same? Could this be the mismatch you wrote about in your mail? The patch should be installed properly though, when I start the script I get the version info “* Vivado v2021.1_AR76780 (64-bit)”. To add, did you perhaps mean `make clean all` instead of `make cleanall`? These two commands give me two different outputs. The latter you suggested just returns “Cleaning targets and IP...” whereas the former actually starts up Vivado and then throws this error: WARNING: [Device 21-436] No parts matched 'ERROR: Invalid target format. Must be <arch>/<device>/<package>/<speedgrade>[/<temperaturegrade>[/<silicon_revision>]] ERROR: Parsed only 2 tokens' ERROR: [Coretcl 2-106] Specified part could not be found. [00:00:06] Current task: Initialization +++ Current Phase: Finished [00:00:06] Process terminated. Status: Failure I will report back on your suggestion of commenting out the line ASAP. I would be very happy to hear feedback from you regarding the errors/warnings above in the meantime. Regards Luca Von: Wade Fife <wade.f...@ettus.com<mailto:wade.f...@ettus.com>> Gesendet: Mittwoch, 5. Juli 2023 06:35 An: Bachmaier, Luca <luca.bachma...@iis.fraunhofer.de<mailto:luca.bachma...@iis.fraunhofer.de>> Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>; Nieland, Michael <michael.niel...@iis.fraunhofer.de<mailto:michael.niel...@iis.fraunhofer.de>> Betreff: Re: [USRP-users] RFNoC Image Builder: two problems with Vitis HLS Hi Luca, Can you try going into the uhd/fpga/usrp3/top/n3xx/ and running `make cleanall` and running the build again? You should not have had to manually upgrade IP unless there was some kind of mismatch somewhere. Perhaps you tried building first without the patch but didn't clean out the old IP that was generated? A version mismatch might explain the HLS error you're getting. If the HLS IP continues to give you problems, you could try commenting out this line. https://github.com/EttusResearch/uhddev/blob/UHD-4.3/fpga/usrp3/lib/hls/Makefile.inc#L7 Wade On Tue, Jul 4, 2023 at 5:50 AM Bachmaier, Luca <luca.bachma...@iis.fraunhofer.de<mailto:luca.bachma...@iis.fraunhofer.de>> wrote: Hello everyone, I'm currently stuck with creating a custom RFNoC bitfile with rfnoc_image_builder. I'm building the image for a USRP N310 and the software I'm using is the following: - Debian 12 - Python 3.11.2 - UHD 4.3.0.0 - Vivado 2021.1 (installed with the additional patch) The command I use to build the image is (I created the file n310_rfnoc_fosphor.yml myself): rfnoc_image_builder -F ~/uhd/fpga -y ~/core_yml/n310_rfnoc_fosphor.yml -t N310_XG After an unsuccessful build, the image builder gets stuck with HLS: ======================================================== BUILDER: Building HLS IP addsub_hls ======================================================== BUILDER: Staging HLS IP in build directory... Waiting for concurrent IP build to finish... (1800s [Ctrl-C to proceed]) I was wondering if there was a way to skip the concurrent IP build, using Ctrl-C only causes the entire rfnoc_image_builder to exit unsuccessfully with: make: *** [Makefile:90: N3X0_IP] Interrupt Waiting for the timeout after 1800 seconds throws the following error that I do not understand at all: source /tools/Xilinx/Vitis_HLS/2021.1/scripts/vitis_hls/hls.tcl -notrace can't read "zny": no such variable while executing "0Nyy-&ur-r$$!$-9-)n$ v t-n q- !$zny-%vz'yn&v! -v s!$zn&v! -zr%%ntr%-n$r-v -&uv%-svyr-" (file "/tools/Xilinx/Vitis_HLS/2021.1/common/scripts/error_message.tcl" line 2) invoked from within Additional info: before that, I had to upgrade two IP cores provided by UHD in Vivado manually because rfnoc_image_builder threw the error: CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci I would be happy to hear any help or pointers to how I could solve this problem. Thank you and regards Luca Bachmaier _______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> To unsubscribe send an email to usrp-users-le...@lists.ettus.com<mailto:usrp-users-le...@lists.ettus.com>
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