Yes, bus_clk is connected to rfnoc_chdr_clk in the RFNoC framework.So in
the YAML it is called "rfnoc_chdr".
Wade
On Wed, Jun 1, 2022 at 3:41 AM Maria Muñoz <mamuk...@gmail.com> wrote:
> Hi Wade,
>
> Thanks for the answer. So "rfnoc_chdr" in the yml file is "bus_clk"?
> In the report timing summary, I see many clocks but there is no
> "rfnoc_chdr", maybe is linked somewhere else in the framework?:
>
> ------------------------------------------------------------------------------------------------
> | Clock Summary
> | -------------
>
> ------------------------------------------------------------------------------------------------
>
> Clock
>
> Waveform(ns) Period(ns) Frequency(MHz)
> -----
>
> ------------ ---------- --------------
> DB0_ADC_DCLK
>
> {0.000 2.500} 5.000 200.000
> DB1_ADC_DCLK
>
> {0.000 2.500} 5.000 200.000
> ETH_CLK
>
> {0.000 4.000} 8.000 125.000
> FPGA_125MHz_CLK
> {0.000
> 4.000} 8.000 125.000
> bus_clk
>
> {0.000 2.667} 5.333 187.500
> bus_clk_div2
>
> {0.000 5.333} 10.667 93.750
> ce_clk
>
> {0.000 2.333} 4.667 214.286
> clkfbout_pcie_clk_gen
>
> {0.000 4.000} 8.000 125.000
> ioport2_clk
>
> {0.000 4.000} 8.000 125.000
> IoPort2Wrapperx/TxClockGenx/TxUseMmcm.ClkFbOutMmcm
> {0.000 4.000} 8.000
> 125.000
> IoPort2Wrapperx/TxClockGenx/TxUseMmcm.ClkOut0Mmcm
> {0.000 2.000} 4.000
> 250.000
> IoTxClock
>
> {0.000 2.000} 4.000 250.000
> IoPort2Wrapperx/TxClockGenx/TxUseMmcm.ClkOut1Mmcm
> {0.000 4.000} 8.000
> 125.000
> ioport2_idelay_ref_clk
>
> {0.000 2.500} 5.000 200.000
> rio40_clk
>
> {0.000 12.500} 25.000 40.000
> FPGA_CLK
>
> {0.000 2.500} 5.000 200.000
> CLK_OUT3_radio_clk_gen
> {0.417
> 1.667} 2.500 400.000
> DB0_DAC_DCI
>
> {0.417 1.667} 2.500 400.000
> DB1_DAC_DCI
>
> {0.417 1.667} 2.500 400.000
> clkfbout_radio_clk_gen
>
> {0.000 2.500} 5.000 200.000
> radio_clk
>
> {0.000 2.500} 5.000 200.000
> radio_clk_2x
>
> {-0.312 0.937} 2.500 400.000
>
> How do I know which clock of those is going to my design?
>
> Kind Regards,
> Maria
>
> El mar, 31 may 2022 a las 22:30, Wade Fife (<wade.f...@ettus.com>)
> escribió:
>
>> Hi Maria,
>>
>> You have the right idea. You should be able to change the srcport from
>> "ce" to "rfnoc_chdr" in the line for your block in the clk_domains section.
>> If that doesn't work, share your YML file and maybe someone can spot the
>> problem.
>>
>> Wade
>>
>> On Tue, May 31, 2022 at 3:47 AM Maria Muñoz <mamuk...@gmail.com> wrote:
>>
>>> Hi all,
>>>
>>> I have generated a custom RFNoC block with rfnocmodtool to be
>>> implemented on X310.
>>> I am using UHD 4.0. toolchain to synthesize it, but I cannot meet timing
>>> with the clock selected (in /icores/yml file, I have select "ce" as the clk
>>> source for my block).
>>> I see that "ce" clock for X310 is 214 MHz and I wondered if I could use
>>> a slower clock for my "ce" from the interface. In the clock reports, there
>>> is a "bus_clk" of 187.5 MHz, which I think is suitable for my design, but
>>> if I select "bus_clk" as clk source for my block in the yml file it gives
>>> an error message:
>>> [ERR] 1 unresolved clk domain(s)
>>> [ERR] block0:ce
>>> [ERR] Please specify the clock(s) to connect
>>>
>>> It is possible to use "bus_clk" as the clock source for my block? Which
>>> files should I modify to use this clock?
>>>
>>> Kind Regards,
>>> Maria
>>> _______________________________________________
>>> USRP-users mailing list -- usrp-users@lists.ettus.com
>>> To unsubscribe send an email to usrp-users-le...@lists.ettus.com
>>>
>>
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