Hi Maria, You have the right idea. You should be able to change the srcport from "ce" to "rfnoc_chdr" in the line for your block in the clk_domains section. If that doesn't work, share your YML file and maybe someone can spot the problem.
Wade On Tue, May 31, 2022 at 3:47 AM Maria Muñoz <mamuk...@gmail.com> wrote: > Hi all, > > I have generated a custom RFNoC block with rfnocmodtool to be implemented > on X310. > I am using UHD 4.0. toolchain to synthesize it, but I cannot meet timing > with the clock selected (in /icores/yml file, I have select "ce" as the clk > source for my block). > I see that "ce" clock for X310 is 214 MHz and I wondered if I could use a > slower clock for my "ce" from the interface. In the clock reports, there is > a "bus_clk" of 187.5 MHz, which I think is suitable for my design, but if I > select "bus_clk" as clk source for my block in the yml file it gives an > error message: > [ERR] 1 unresolved clk domain(s) > [ERR] block0:ce > [ERR] Please specify the clock(s) to connect > > It is possible to use "bus_clk" as the clock source for my block? Which > files should I modify to use this clock? > > Kind Regards, > Maria > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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