Hi all, I was also refreshing my memory on how this works. dds_timed is used by the DUC. For the DDC, I think the line you need is here:
https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/lib/rfnoc/ddc.v#L115 Also, I think you need to change this line too, which affects both DDC and DUC: https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/lib/rfnoc/axi_tag_time.v#L48 It looks like a mistake that it's not driven by the same parameter, but I need to look at it more closely. Maybe @Brian Padalino <bpadal...@gmail.com> can confirm. Wade On Tue, May 31, 2022 at 3:48 PM Marcus D. Leech <patchvonbr...@gmail.com> wrote: > On 2022-05-31 16:43, Brian Padalino wrote: > > On Tue, May 31, 2022 at 3:42 PM <ri28...@mit.edu> wrote: > >> Hi, >> >> I’m playing around with frequency hopping on a USRP x310 with a UBX 160 >> daughterboard. In particular, I want to hop to a few different frequencies >> that are integer multiples of my master clock rate and well within the >> daughtercard bandwidth rapidly (hopping every ~200 us). I know the hopping >> schedule well in advance, but as described in the timed command >> documentation ( >> https://kb.ettus.com/Synchronizing_USRP_Events_Using_Timed_Commands_in_UHD) >> the default command queue depth is only 5 slots per IP core. Given that the >> Linux kernel scheduler uses a ~1ms jiffy, it’s rather difficult to send new >> timed command accurately when a queue slot is available. It would be much >> easier if I could batch up the tune commands. >> >> Is there a way for me to build a default X310 FPGA image but increase the >> DDC and DUC queue size? I have access to a Vivado license. Is there an >> example tutorial somewhere? Even better, are the DUC/DDC queue depths >> parametrized in the build scripts? >> > > I think the 5 here in the CMD_FIFO_SIZE means 2^5 = 32 slots: > > > https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/lib/rfnoc/dds_timed.v#L292 > > Though I am unsure how many words are written at a time for changing the > frequency. It seems like just a single settings register, but maybe > there's more in the implementation? > > Have you tried just writing out the frequencies you want to change and > seeing if you get automatic holdoff as the command FIFO fills up? > > Either way, you should be able to just make that CMD_FIFO_SIZE deeper > (note: it's the log2, so 8 should be 256 deep). Let us know how it works > out? > > Brian > > The DDC and DUC tuning words would be an increment value for the > phase-accumulator, I think. Which is ca 32 bits on GEN2 implementations > from fuzzy and distant memory. > > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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