Hi, I’m playing around with frequency hopping on a USRP x310 with a UBX 160 daughterboard. In particular, I want to hop to a few different frequencies that are integer multiples of my master clock rate and well within the daughtercard bandwidth rapidly (hopping every \~200 us). I know the hopping schedule well in advance, but as described in the timed command documentation (https://kb.ettus.com/Synchronizing_USRP_Events_Using_Timed_Commands_in_UHD) the default command queue depth is only 5 slots per IP core. Given that the Linux kernel scheduler uses a \~1ms jiffy, it’s rather difficult to send new timed command accurately when a queue slot is available. It would be much easier if I could batch up the tune commands.
Is there a way for me to build a default X310 FPGA image but increase the DDC and DUC queue size? I have access to a Vivado license. Is there an example tutorial somewhere? Even better, are the DUC/DDC queue depths parametrized in the build scripts? Thanks, Richard
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
