If you change the UHD printout from MHz to Hz, it looks like the step
size is around 0.4 Hz at 23 MHz (and MCR doesn't have to be an integer).
Using a DVB-T2 sample rate of (8000000.0 * 5) / 7 and adding 0.01 Hz for
each run (with 4X MCR)
[INFO] [B200] Asking for clock rate 22857142.977143 Hz... ((8000000.0 *
5) / 7 + 0.03)
[INFO] [B200] Actually got clock rate 22857143.028110 Hz.
[INFO] [B200] Asking for clock rate 22857143.017143 Hz... ((8000000.0 *
5) / 7 + 0.04)
[INFO] [B200] Actually got clock rate 22857143.028110 Hz.
[INFO] [B200] Asking for clock rate 22857143.057143 Hz... ((8000000.0 *
5) / 7 + 0.05)
[INFO] [B200] Actually got clock rate 22857143.028110 Hz.
[INFO] [B200] Asking for clock rate 22857143.097143 Hz... ((8000000.0 *
5) / 7 + 0.06)
[INFO] [B200] Actually got clock rate 22857143.028110 Hz.
[INFO] [B200] Asking for clock rate 22857143.137143 Hz... ((8000000.0 *
5) / 7 + 0.07)
[INFO] [B200] Actually got clock rate 22857143.028110 Hz.
[INFO] [B200] Asking for clock rate 22857143.177143 Hz... ((8000000.0 *
5) / 7 + 0.08)
[INFO] [B200] Actually got clock rate 22857143.028110 Hz.
[INFO] [B200] Asking for clock rate 22857143.217143 Hz... ((8000000.0 *
5) / 7) + 0.09
[INFO] [B200] Actually got clock rate 22857143.028110 Hz.
[INFO] [B200] Asking for clock rate 22857143.257143 Hz... ((8000000.0 *
5) / 7) + 0.10
[INFO] [B200] Actually got clock rate 22857143.427032 Hz.
The claim of "any sample rate" is not that far off.
Ron
On 10/28/20 18:54, Marcus D. Leech via USRP-users wrote:
On 10/28/2020 09:07 PM, Barry Duggan via USRP-users wrote:
Hi Neel,
Thanks for the quick response! As a clarification:
- for half-duplex operation, is the receiver muted (and protected)
during transmit?
- I could not find the sample rates on your website.
https://files.ettus.com/manual/page_usrp_b200.html#b200_mcr
It says "ANY value between 5MHz and 61.44MHz", but in reality, it has
to be integer, and there are rates that don't work because of the
PLL architecture--I just can't remember what those restrictions are.
But even if the step size is 10kHz, with integer decimation
implemented in the FPGA, that's really a lot of different supported
sample rates.
Normally UHD will pick a master clock rate for you, given the desired
sample rate. It will try to pick the highest multiple of your
desired sample rate that is also a a multiple of two. Sometimes,
you'd rather it not try to be "clever", so you specify the master clock
rate as a device argument and set sample rates accordingly.
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