Hello, Is there any (somewhat straight forward) way to debug timed commands on the FPGA? In particular, I want to know: 1.) if any timed command is not executed as timed command but right away (because it had a timestamp but the command was late so it was executed right away) 2.) if any command queue overruns 3.) Any other sort of information that causes timed commands to misbehave
I use "tx_command" for USRP Sink to send timed commands. The "tx_command" tags are injected with an embedded python block. I use "Tag Debug" and save all tags to a text file. Works. Then, in exactly the same block diagram, I replace the embedded python block with my C++ implementation that generates tags. Suddenly, some timed commands do not execute at the right moment any more (these are just few and consistent across re-runs and reboots). However, the tags generated by boths blocks are absolutely IDENTICAL! A diff between the "tx_command" outputs results in NO differences. Hence I need to know what the FPGA actually processes in both cases. Thanks Lukas _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
