Hi Jeff, For UHD 3.15, I believe that issue has been fixed. Check out the UHD-3.15.LTS branch and let me know if you still have an issue building.
For UHD 3.14, check out the UHD-3.14 branch. Using the branches above, I was able to successfully build an image using your uhd_image_builder command (without the -g option) for both UHD 3.15 and UHD 3.14. Jonathon On Wed, May 20, 2020 at 8:35 PM Hodges, Jeff via USRP-users < usrp-users@lists.ettus.com> wrote: > Can someone please tell me what version of uhd and rfnoc are compatible > for building an image on Ubuntu 18.04? > > > > I cannot get any of the UHD releases to properly build a standard rfnoc > image. > > > > sudo ./uhd_image_builder.py fft ddc duc -g -t X310_RFNOC_HG -c -d X310 > --fill-with-fifos > > > > I installed vivado 2018.3 with uhd 3.15.0.0 and get the error: > > > > ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4 > has multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and > bus_clk_gen/inst/clkout4_buf/O. > > ERROR: [DRC MDRV-1] Multiple Driver Nets: Net > radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has > multiple drivers: > radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q, > and > ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q. > > > > > > I installed vivado 2017.4 with uhd 3.14.1.1 and get this error: > > > > BUILDER: Releasing IP location: > /home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/aurora_64b66b_pcs_pma > > Using parser configuration from: > /home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/dev_config.json > > [00:00:00] Executing command: vivado -mode batch -source > /home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build_x300.tcl -log > build.log -journal x300.jou > > CRITICAL WARNING: [filemgmt 20-1440] File > '/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v' > already exists in the project as a part of sub-design file > '/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'. > Explicitly adding the file outside the scope of the sub-design can lead to > unintended behaviors and is not recommended. > > [00:00:29] Current task: Initialization +++ Current Phase: Starting > > [00:00:29] Current task: Initialization +++ Current Phase: Finished > > [00:00:29] Executing Tcl: synth_design -top x300 -part xc7k410tffg900-2 > -verilog_define BUILD_1G=1 -verilog_define BUILD_10G=1 -verilog_define > SFP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define RFNOC=1 > -verilog_define X310=1 -verilog_define GIT_HASH=32'hfbb85bdf > > [00:00:29] Starting Synthesis Command > > ERROR: [Synth 8-439] module 'ddr3_32bit' not found > [/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/x300.v:1191] > > ERROR: [Synth 8-285] failed synthesizing module 'x300' > [/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/x300.v:20] > > ERROR: [Common 17-69] Command failed: Synthesis failed - please see the > console or run log file for details > > [00:08:36] Current task: Synthesis +++ Current Phase: Starting > > [00:08:36] Current task: Synthesis +++ Current Phase: Finished > > [00:08:36] Process terminated. Status: Failure > > > > > > Any advice is greatly appreciated. > > > > Thanks, > > > > Jeff > > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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