Cherif,

Great news! Congrats on the fix!

Cheers,
Daniel

On Mon, Oct 7, 2019 at 9:48 AM Cherif Diouf via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Daniel,
>
>
> The problem was finally solved. It was from both my software and my
> hardware development.
>
> -> in fact in the software I used the set_time_next_pps() call from the
> device3 object to synchronize the vitatime counter with the PPS signal, but
> later on I would also create a rfnoc_streamer object to be able to use
> the rf frontend. This would somewhat modify the vitatime value and
> desynchronize my local counter with the  vitatime counter causing random
> offset between the two counters.
>
> -> The second problem was linked to the cvita_hdr_encoder  which was not
> properly set, Leading the frontend to transmit asap, I guess.
>
>
> So from both these issues I could be from time to time off by one sample/5
> ns at the transmitter.
>
> Now that's old story !
>
>
> Many thanks
>
>
> Cherif
>
>
>
>
> __________________
>
> Fabian, I had a hunch it was just the 3.3V part--thanks for clarifying!
>
> Cherif, the DAC interface timing (and for that matter, the ADC timing)
> should be fairly tight. What you're seeing is expected and matches the
> numbers we designed it to. The FPGA constraints are intentionally tight to
> provide some extra margin at the DAC. Since this is all in the same X310,
> you could start by isolating the various components of the design using the
> front-panel GPIO connector. Run a trigger from each of your custom blocks
> to the GPIO and see if they line up on a scope. If they don't, then you
> might have a baseband timing issue (with how timed commands are interacting
> with your blocks). If they line up, then it points to a timing failure in
> the DAC.
>
> -Daniel
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>


-- 

Daniel Jepson

Digital Hardware Engineer

National Instruments



O: +1.512.683.6163

daniel.jep...@ni.com
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