Here's a modified add-only block. You'll have to make a matching .xml
descriptor and GRC block (if you're using gr-ettus).
Probably it would be a super useful thing to have an add/sub block, instead
of an addsub block. A register-controlled mux to select which operation you
want. I'll think about adding that to the Theseus Cores project.
Nick
On Fri, Sep 6, 2019 at 3:18 PM d.des via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Nick-
> Could you share the tricks to remove one of the output ports? I don't
> I'm having similar issues with my modified addsub block and don't have
> enough room on the e310 fpga for extra fifos. It's not obvious from the
> noc_block_addsub code, the use of splitstream and dummy variables is
> very confusing.
>
> Tnx,
> Dave (and I'm sure many others, based on threads I've seen in searches)
>
> ________________________________
> From: Nick Foster <bistromath at gmail.com>
> Sent: Tuesday, September 3, 2019 11:45:46 PM
> To: Quadri,Adnan <adnan.quadri at louisville.edu>
> Cc: usrp-users at lists.ettus.com <usrp-users at lists.ettus.com>
> Subject: Re: [USRP-users] Addsub HLS Block Error
>
> That shouldn't be. Even if you connect both outputs to the host?
>
> I admit I got fed up with it in my own application (don't want both
> streams going into the host) and just modified the addsub block to be
> an add-only block.
>
> On Tue, Sep 3, 2019 at 8:43 PM Quadri,Adnan <adnan.quadri at
> louisville.edu<mailto:adnan.quadri at louisville.edu>> wrote:
> I tried connecting one Signal Source block to both the inputs of addsub
> block. It still throws the same error.
>
> Adnan
> ________________________________
> From: Nick Foster <bistromath at gmail.com<mailto:bistromath at
> gmail.com>>
> Sent: Tuesday, September 3, 2019 11:40:05 PM
> To: Quadri,Adnan <adnan.quadri at louisville.edu<mailto:adnan.quadri at
> louisville.edu>>
> Cc: usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>
> <usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>>
> Subject: Re: [USRP-users] Addsub HLS Block Error
>
> Oh, I see. You have separate sources connected to the same addsub
> block. It's telling you that you need to use timed stream commands to
> start the stream, or else you will see undefined behavior. Personally I
> think that error should be demoted to a warning -- anyone from Ettus
> want to chime in?
>
> On Tue, Sep 3, 2019 at 3:53 PM Quadri,Adnan <adnan.quadri at
> louisville.edu<mailto:adnan.quadri at louisville.edu>> wrote:
> Hello,
>
> Thank you for your prompt response. I have connected both the addsub
> output to two QT Gui Sink but I still get the same error. I have the
> Copy block in the middle as well.
>
> I am attaching a screenshot of my flowgraph. I tried with different
> USRP sources/Signal Sources as well. But it is the same error.
>
> Thanks,
> Adnan
>
> ________________________________
> From: Nick Foster <bistromath at gmail.com<mailto:bistromath at
> gmail.com>>
> Sent: Tuesday, September 3, 2019 3:57 PM
> To: Quadri,Adnan <adnan.quadri at louisville.edu<mailto:adnan.quadri at
> louisville.edu>>
> Cc: usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>
> <usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>>
> Subject: Re: [USRP-users] Addsub HLS Block Error
>
> I ran into this the other day and it's independent of the HLS component
> of the addsub block (since the interface is identical). You need to
> connect both outputs of the addsub block to something, even a null
> sink. I'm pretty sure this wasn't the intended behavior and also pretty
> sure that it wasn't like this last time I checked (which was more than
> a year ago), so maybe it should be filed as a bug.
>
> Nick
>
> On Tue, Sep 3, 2019 at 1:48 PM Quadri,Adnan via USRP-users <usrp-users
> at lists.ettus.com<mailto:usrp-users at lists.ettus.com>> wrote:
> Hello,
>
> We are trying to run the RFNoC addsub HLS block.
>
> I was able to build the FPGA Image and made sure in the noc_block
> verilog code to point to the HLS implementation for addsub block on
> RFNoC as opposed to the verilog/VHDL implementation.
>
> But when we run the example Flowgraph with two signal source as input
> to the two inputs for addsub block on GRC, we get the following error -
>
> ERROR:
> thread[thread-per-block[4]: <block uhd_rfnoc_AddSub (1)>]:
> RuntimeError: Invalid recv stream command - stream now on multiple
> channels in a single streamer will fail to time align.
>
> Does this have anything to do with the C++ code for HLS implementation
> or is it a problem at UHD level?
>
> Thanks,
> Adnan
> _______________________________________________
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//
// Copyright 2015 Ettus Research LLC
// Copyright 2018 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
`default_nettype none
module noc_block_add #(
parameter NOC_ID = 64'hADD1_0000_0000_0000,
parameter STR_SINK_FIFOSIZE = 11)
(
input wire bus_clk, input wire bus_rst,
input wire ce_clk, input wire ce_rst,
input wire [63:0] i_tdata, input wire i_tlast, input wire i_tvalid, output wire i_tready,
output wire [63:0] o_tdata, output wire o_tlast, output wire o_tvalid, input wire o_tready,
output wire [63:0] debug
);
localparam MTU = 10;
/////////////////////////////////////////////////////////////
//
// RFNoC Shell
//
////////////////////////////////////////////////////////////
wire [63:0] cmdout_tdata, ackin_tdata;
wire cmdout_tlast, cmdout_tvalid, cmdout_tready, ackin_tlast, ackin_tvalid, ackin_tready;
wire [127:0] str_sink_tdata;
wire [1:0] str_sink_tlast, str_sink_tvalid, str_sink_tready;
wire [63:0] str_src_tdata;
wire str_src_tlast, str_src_tvalid, str_src_tready;
wire [31:0] in_tdata[0:1];
wire [127:0] in_tuser[0:1];
wire [1:0] in_tlast, in_tvalid, in_tready;
wire [31:0] out_tdata;
wire [127:0] out_tuser;
wire out_tlast, out_tvalid, out_tready;
wire clear_tx_seqnum, clear_tx_seqnum_bclk;
wire [15:0] src_sid[0:1], next_dst_sid;
synchronizer #(.INITIAL_VAL(1'b0), .WIDTH(1)) clear_tx_sync_i (
.clk(bus_clk), .rst(1'b0), .in(clear_tx_seqnum), .out(clear_tx_seqnum_bclk));
// FIXME this needs an axi_wrapper, it talks 32bit data
noc_shell #(
.NOC_ID(NOC_ID),
.STR_SINK_FIFOSIZE({2{STR_SINK_FIFOSIZE[7:0]}}),
.MTU({2{MTU[7:0]}}),
.INPUT_PORTS(2),
.OUTPUT_PORTS(1))
noc_shell (
.bus_clk(bus_clk), .bus_rst(bus_rst),
.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
// Compute Engine Clock Domain
.clk(ce_clk), .reset(ce_rst),
// Control Sink
.set_data(), .set_addr(), .set_stb(), .set_time(), .set_has_time(),
.rb_stb(2'b11), .rb_data(128'd0), .rb_addr(),
// Control Source
.cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready),
.ackin_tdata(ackin_tdata), .ackin_tlast(ackin_tlast), .ackin_tvalid(ackin_tvalid), .ackin_tready(ackin_tready),
// Stream Sink
.str_sink_tdata(str_sink_tdata), .str_sink_tlast(str_sink_tlast), .str_sink_tvalid(str_sink_tvalid), .str_sink_tready(str_sink_tready),
// Stream Source
.str_src_tdata(str_src_tdata), .str_src_tlast(str_src_tlast), .str_src_tvalid(str_src_tvalid), .str_src_tready(str_src_tready),
.clear_tx_seqnum(clear_tx_seqnum), .src_sid({src_sid[1],src_sid[0]}), .next_dst_sid(next_dst_sid),
.resp_in_dst_sid(/* Unused */), .resp_out_dst_sid(/* Unused */),
.debug(debug));
genvar i;
generate
for (i=0; i<2; i=i+1)
chdr_deframer_2clk deframer (
.pkt_clk(bus_clk), .pkt_rst(bus_rst | clear_tx_seqnum_bclk),
.samp_clk(ce_clk), .samp_rst(ce_rst | clear_tx_seqnum),
.i_tdata(str_sink_tdata[i*64+63:i*64]), .i_tlast(str_sink_tlast[i]), .i_tvalid(str_sink_tvalid[i]), .i_tready(str_sink_tready[i]),
.o_tdata(in_tdata[i]), .o_tuser(in_tuser[i]), .o_tlast(in_tlast[i]), .o_tvalid(in_tvalid[i]), .o_tready(in_tready[i]));
endgenerate
reg sof_in = 1'b1;
always @(posedge ce_clk) begin
if (ce_rst | clear_tx_seqnum) begin
sof_in <= 1'b1;
end
if (in_tvalid[0] & in_tready[0]) begin
if (in_tlast[0]) begin
sof_in <= 1'b1;
end else begin
sof_in <= 1'b0;
end
end
end
wire header_fifo_i_tvalid = sof_in & in_tvalid[0] & in_tready[0];
reg [127:0] in_tuser_reg;
always @(posedge ce_clk) begin
if (ce_rst) begin
in_tuser_reg <= 'b0;
end
else
begin
if (header_fifo_i_tvalid) begin
in_tuser_reg <= in_tuser[0];
end
end
end
assign out_tuser = { in_tuser_reg[127:96], src_sid[0], next_dst_sid, in_tuser_reg[63:0] };
addsub #(.WIDTH(16)) inst_addsub (
.clk(ce_clk), .reset(ce_rst),
.i0_tdata(in_tdata[0]), .i0_tlast(in_tlast[0]), .i0_tvalid(in_tvalid[0]), .i0_tready(in_tready[0]),
.i1_tdata(in_tdata[1]), .i1_tlast(in_tlast[1]), .i1_tvalid(in_tvalid[1]), .i1_tready(in_tready[1]),
.sum_tdata(out_tdata), .sum_tlast(out_tlast), .sum_tvalid(out_tvalid), .sum_tready(out_tready),
.diff_tready(out_tready));
chdr_framer_2clk #(
.SIZE(MTU))
framer (
.pkt_clk(bus_clk), .pkt_rst(bus_rst | clear_tx_seqnum_bclk),
.samp_clk(ce_clk), .samp_rst(ce_rst | clear_tx_seqnum),
.i_tdata(out_tdata), .i_tuser(out_tuser), .i_tlast(out_tlast), .i_tvalid(out_tvalid), .i_tready(out_tready),
.o_tdata(str_src_tdata), .o_tlast(str_src_tlast), .o_tvalid(str_src_tvalid), .o_tready(str_src_tready));
endmodule
`default_nettype wire
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