Nick-
Could you share the tricks to remove one of the output ports? I don't
I'm having similar issues with my modified addsub block and don't have
enough room on the e310 fpga for extra fifos. It's not obvious from the
noc_block_addsub code, the use of splitstream and dummy variables is
very confusing.

Tnx,
Dave (and I'm sure many others, based on threads I've seen in searches)

________________________________
From: Nick Foster <bistromath at gmail.com>
Sent: Tuesday, September 3, 2019 11:45:46 PM
To: Quadri,Adnan <adnan.quadri at louisville.edu>
Cc: usrp-users at lists.ettus.com <usrp-users at lists.ettus.com>
Subject: Re: [USRP-users] Addsub HLS Block Error

That shouldn't be. Even if you connect both outputs to the host?

I admit I got fed up with it in my own application (don't want both
streams going into the host) and just modified the addsub block to be
an add-only block.

On Tue, Sep 3, 2019 at 8:43 PM Quadri,Adnan <adnan.quadri at
louisville.edu<mailto:adnan.quadri at louisville.edu>> wrote:
I tried connecting one Signal Source block to both the inputs of addsub
block. It still throws the same error.

Adnan
________________________________
From: Nick Foster <bistromath at gmail.com<mailto:bistromath at
gmail.com>>
Sent: Tuesday, September 3, 2019 11:40:05 PM
To: Quadri,Adnan <adnan.quadri at louisville.edu<mailto:adnan.quadri at
louisville.edu>>
Cc: usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>
<usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>>
Subject: Re: [USRP-users] Addsub HLS Block Error

Oh, I see. You have separate sources connected to the same addsub
block. It's telling you that you need to use timed stream commands to
start the stream, or else you will see undefined behavior. Personally I
think that error should be demoted to a warning -- anyone from Ettus
want to chime in?

On Tue, Sep 3, 2019 at 3:53 PM Quadri,Adnan <adnan.quadri at
louisville.edu<mailto:adnan.quadri at louisville.edu>> wrote:
Hello,

Thank you for your prompt response. I have connected both the addsub
output to two QT Gui Sink but I still get the same error. I have the
Copy block in the middle as well.

I am attaching a screenshot of my flowgraph. I tried with different
USRP sources/Signal Sources as well. But it is the same error.

Thanks,
Adnan

________________________________
From: Nick Foster <bistromath at gmail.com<mailto:bistromath at
gmail.com>>
Sent: Tuesday, September 3, 2019 3:57 PM
To: Quadri,Adnan <adnan.quadri at louisville.edu<mailto:adnan.quadri at
louisville.edu>>
Cc: usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>
<usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>>
Subject: Re: [USRP-users] Addsub HLS Block Error

I ran into this the other day and it's independent of the HLS component
of the addsub block (since the interface is identical). You need to
connect both outputs of the addsub block to something, even a null
sink. I'm pretty sure this wasn't the intended behavior and also pretty
sure that it wasn't like this last time I checked (which was more than
a year ago), so maybe it should be filed as a bug.

Nick

On Tue, Sep 3, 2019 at 1:48 PM Quadri,Adnan via USRP-users <usrp-users
at lists.ettus.com<mailto:usrp-users at lists.ettus.com>> wrote:
Hello,

We are trying to run the RFNoC addsub HLS block.

I was able to build the FPGA Image and made sure in the noc_block
verilog code to point to the HLS implementation for addsub block on
RFNoC as opposed to the verilog/VHDL implementation.

But when we run the example Flowgraph with two signal source as input
to the two inputs for addsub block on GRC, we get the following error -

ERROR:
thread[thread-per-block[4]: <block uhd_rfnoc_AddSub (1)>]:
RuntimeError: Invalid recv stream command - stream now on multiple
channels in a single streamer will fail to time align.

Does this have anything to do with the C++ code for HLS implementation
or is it a problem at UHD level?

Thanks,
Adnan
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