Ian and Jason, So if I understand Although if it possible to work with different clock domains, and while some examples are available for such scenario, it would be preferable to keep working with the same 200 MHz reference and only switch to another frequency only when it is really needed.
Many thanks for the info. Cherif ________________________________ From: Ian Buckley <i...@ionconcepts.com> Sent: donderdag 28 februari 2019 17:36 To: Cherif Diouf <c.e.v.di...@tudelft.nl> Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] Hardware clocks, X310 Cherif, 1) Changing the radio clock frequency is not simple and would leave you an immense amount of knock on problems to address. 2) ADC and DAC are tightly coupled to the radio clk, they run on low jitter versions of the same clock. 3) Absolutely, and that is the beauty of streaming style packet buses like the AXI4 stream protocol that the X310 is built around. It's a relatively easy task to cross this type of bus into a different clock domain, do work on the payload, and cross it back. The modular RTL code supplied by Ettus already contains all the functional blocks you would need to do this. So saying that it's always a good thing to minimize the number of clock domains in a design as it adds significant overhead and complexity, not to mention a verification burden. Evaluate hard if you really need another frequency, especially when its an integer fraction of a clock that already exists. 200MHz is not a hard frequency to attain in Virtex-7 with well designed logic. -Ian From: Jason Matusiak <ja...@gardettoengineering.com> Sent: donderdag 28 februari 2019 17:38 To: usrp-users@lists.ettus.com; Cherif Diouf <c.e.v.di...@tudelft.nl> Subject: Re: Hardware clocks, X310 Cherif. I will attempt to take a stab at a few of your questions. Don't take my answers as 100% right.... 1 - All the blocks run at the same rate, but I am pretty sure you can implement an MMCM within your block to lower the rate for your needs and then back up to the crossbar rate. Don't quote me, but I feel like I had this conversation with someone a few years back on the mailing list. 2 - The ADC/DAC are tied to the master clock rate (in the case of the X310, either 186.32MHz, or 200MHz) 3 - I don't believe so unless you do what I mentioned in the first comment. All that said, I believe a lot of stuff can be tweaked under the hood, but it is hard to say what that will break, and it isn't exactly supported. ________________________________ From: USRP-users <usrp-users-boun...@lists.ettus.com<mailto:usrp-users-boun...@lists.ettus.com>> on behalf of Cherif Diouf via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> Sent: Thursday, February 28, 2019 10:05 AM To: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: [USRP-users] Hardware clocks, X310 Hello guys, I am a researcher working with the X310 USRP. I have a couple of questions regarding the Hardware clocks. The bus_clock and radio_clk are by default respectively set at 166 MHz and 200 MHz. And if I am right the crossbar clock ce_clk is also at 200 MHz. Is there a solution to bring it down to ce_clk = 50 MHz, in that case 1) Does it mean that all the Kintex XC410T blocks will run at 50 MHz ? Is this safe? 2) What about the ADC and DAC and their sampling clock? 3) Finally can we have different RFnoc blocks running at different clock frequencies and still have the crossbar running at a given clock frequency? Best Regards Cherif
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