Hey Carlos,
On Tue, Dec 4, 2018 at 1:16 PM Carlos Alberto Ruiz Naranjo <
[email protected]> wrote:
> Hi Brian,
>
> I have finished the DDC block 1:8 and it works perfectly!! :) :)
>
Congratulations!
>
> Now I am in my final step, a 2:16 DDC block:
> - Channels 0:7 connected to input 0.
> - Channels 8:15 connected to input 1.
>
> The verilog module works, but I have a problem with the UHD driver. I have
> timeout on chan 8,9,10...15.
> When I use GNURadio Signal Source it runs fine, but when I use rfnoc Radio
> block no.
>
> I have tried (device3_io_impl.cpp) :
>
> ...
> // Update args so args.args is always valid for this particular
> channel:
> args.args = chan_args[stream_i];
> size_t mb_index = block_id.get_device_no();
> size_t suggested_block_port = args.args.cast<size_t>("block_port",
> rfnoc::ANY_PORT);
> // printf("Puerto: %i\n",suggested_block_port);
> // change
> // size_t radio_block_port = args.args.cast<size_t>("radio_port",
> rfnoc::ANY_PORT) ;
> size_t radio_block_port = 0;
>
> if (stream_i<8){
> radio_block_port = 0;
> }
> else{
> radio_block_port = 1;
> }
> ...
>
> (( I recognize that I am not an expert on the driver)) :/
>
Unfortunately, you've gone outside my experience and knowledge. Good luck,
and please keep us posted if you are able to figure out how to get it to
work. It sounds like a fun and interesting block you're working on.
Brian
PS - Do you plan on open sourcing the block?
>
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