Hello Brian, Thank you very much for answering, I am spending a lot of time on this and I do not see the way out.
I am following your advice, I have removed the 3 inputs of FPGA code, but I am having problems. I have doubts with: - str_sink_tvalid and str_sink_tready[line 165] - str_src_tready [line 166] - sample_in_tready [line 297] - sample_out_tready [line 301] When I run DDC rfnoc test with this changes fails. This is the rfnoc DDC modified code. https://pastebin.com/txTXCMyc Thank you!!!!!! :) :) El lun., 26 nov. 2018 a las 19:36, Brian Padalino (<bpadal...@gmail.com>) escribió: > On Mon, Nov 26, 2018 at 12:14 PM Carlos Alberto Ruiz Naranjo via > USRP-users <usrp-users@lists.ettus.com> wrote: > >> Hello, >> >> I have customized the rfnoc DDC. I have: >> >> - 4 inputs (0,1,2,3). >> - 4 outputs (0,1,2,3). >> - 4 independently tunable DDCs. >> - Input 0 connected to outputs 0,1,2,3. >> - Input 1,2,3 disconnected. >> >> I attach a diagram. >> >> But I do not know how to connect inputs 1,2,3 to a null source for . Any >> ideas? >> > > If you don't plan on using those inputs for anything, just don't make them. > > Make 1 input, 4 outputs. > > Brian >
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