Hey Carlos, On Tue, Nov 27, 2018 at 6:18 PM Carlos Alberto Ruiz Naranjo < carlosruiznara...@gmail.com> wrote:
> Hello Brian, > > Thank you very much for answering, I am spending a lot of time on this and > I do not see the way out. > > I am following your advice, I have removed the 3 inputs of FPGA code, but > I am having problems. > > I have doubts with: > > - str_sink_tvalid and str_sink_tready[line 165] > - str_src_tready [line 166] > - sample_in_tready [line 297] > - sample_out_tready [line 301] > I solved this by having N axi_wrappers - one for each output I wanted. I then only wire the inputs into axi_wrapper0 and no inputs into the other axi_wrappers - just the outputs. I then send the stream tdata from axi_wrapper0 to an nsplit_stream_fifo which does the 1:N conversion for me. I have 8 outputs, and I had to make changes to UHD to support writing to the appropriate ports inside of the block, but that is a different issue altogether. Note that it's very easy to fill up the FPGA using multiple output ports. Lots of FIFOs get instantiated. Good luck! Brian >
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