Hi Sylvain, You are absolutely correct. We are looking at splitting the axi_packet_gate into a buffer and a packet gate. That should effectively reduce the address FIFO to a reasonable size and reduce the resource usage back to reasonable levels.
Regards, Michael On Thu, Oct 4, 2018 at 4:10 AM Sylvain Munaut <246...@gmail.com> wrote: > Hi Michael, > > > Thank you for letting us know. That is quite a jump in utilization. We > will take a look when we have some time. > > > > We did recently make recent bug fixes in axi_packet_gate. It looks like > that, and possibly other changes, inadvertently increased resource > utilization more than expected for B200. Our priority is always first to > make sure the FPGA images successfully build with the bug fixes so we can > get those bug fixes out to users as soon as possible. We do try to > minimize resource utilization, but that is a secondary priority. > > AFAICT, it's all due to the new "address FIFO". But that FIFO seems to > be setup to be unreasonably large. > > I mean it can store as many addresses as data words ... while AFAICT > it only has to store one address per packet in the buffer, so reducing > it to say 32 entries should be enough. This way 6 bits can fit in 1 > CLB using 32x2 distrams instead of using block rams. > > Cheers, > > Sylvain >
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