Hi Silvain, Thank you for letting us know. That is quite a jump in utilization. We will take a look when we have some time.
We did recently make recent bug fixes in axi_packet_gate. It looks like that, and possibly other changes, inadvertently increased resource utilization more than expected for B200. Our priority is always first to make sure the FPGA images successfully build with the bug fixes so we can get those bug fixes out to users as soon as possible. We do try to minimize resource utilization, but that is a secondary priority. Regards, Michael On Wed, Oct 3, 2018 at 3:19 AM Sylvain Munaut via USRP-users < usrp-users@lists.ettus.com> wrote: > And the culprit is axi_packet_gate .... > It actually uses so much more BRAMs than the MAP process replaces some > of the inferred BRAM by inferred dist ram instead to fit everything in > a B200. > > Not sure why this now needs some much more resources than it did before. > > Cheers, > > Sylvain > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
_______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
