Dear users…
We have a question regarding the 1pps time stamping. We don’t know exactly where it is best to ask this question, so please advise if needed.: We use a B200 board. When we do a “sample tick reset” relative to 1pps using virtual void set_time_next_pps(const time_spec_t &time_spec, size_t mboard = ALL_MBOARDS) = 0; what is the delay from the sample is actually taken on the ADC to the place where the 1pps timestamp is attached to the samples ? Is there a compensation for this delay? and next is this delay fixed for a given configuration or does it depend on fifo latency between clock domains (adc-clock to fpga-clock) i.e. it becomes stochastic ? And finally how to calculate this delay (if stochastic the worst case delay) from sample rates, fpga clocks and fifo depths? /fabric
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