On 04/26/2018 09:31 AM, Thomas via USRP-users wrote:
Dear users…
We have a question regarding the 1pps time stamping. We don’t know
exactly where it is best to ask this question, so please advise if
needed.:
We use a B200 board.
When we do a “sample tick reset” relative to 1pps using
virtualvoidset_time_next_pps(consttime_spec_t&time_spec, size_tmboard=
ALL_MBOARDS) = 0;
what is the delay from the sample is actually taken on the ADC to the
place where the 1pps timestamp is attached to the samples ? Is there a
compensation for this delay? and next is this delay fixed for a given
configuration or does it depend on fifo latency between clock domains
(adc-clock to fpga-clock) i.e. it becomes stochastic ?
And finally how to calculate this delay (if stochastic the worst case
delay) from sample rates, fpga clocks and fifo depths?
/fabric
There's a master-clock-rate-resolution TOD clock that is reset by the
set_time_next_pps() call, and the TOD clock is used to add a timestamp to
sample packets as they're framed for transmission across USB.
There will be a fixed delay for any given configuration, including
things like filter group delays and so on. But it will be repeatable,
and can be
measured and compensated for on the software side.
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
