Hi everyone! For the FPGA source code written for b210, I noticed that the input to the GPIF_D that is 32 bits, and then in went through some FIFOs up converting to 64 bits and then down to 12 bits output (tx_codec_d).
May I know what is the purpose of up converting and then down convert again? Will it affect anything if I remove all these and just connect GPIF_D (32 bits) input and take 12 bits MSB (truncation) and connect directly to tx_codec_d (12 bits) ? Thanks in advance!
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