Editing the python file and pointing to the top OOT directory fixed the issue thank you.
________________________________ From: EJ Kreinar <ejkrei...@gmail.com> Sent: Wednesday, October 4, 2017 5:19:55 PM To: Nicolas Cuervo Cc: Avila, Jose A; usrp-users@lists.ettus.com Subject: Re: [USRP-users] Error creating RFNoC FPGA image with OOT module Hi Jose, You've encountered a new feature of the uhd-fpga build process. If your OOT repo has a Makefile.inc, the uhd_image_builder.py script will point to those makefiles in the OOT repo. This is especially useful for synthesizing Xilinx IP or HLS cores. (See the Makefile.inc files here for a dummy example: https://github.com/ejk43/rfnoc-ootexample/tree/master/rfnoc) This is a feature that is (as of today, Oct 2017) not currently supported with rfnocmodtool, so it's somewhat "advanced", but we'd like to add this capability to rfnocmodtool soon :) It looks like your noc_block_twochannelsiggen is just not getting found. This is probably an issue with the Makefiles in your OOT repo. For example, this configuration might work: 1. <gnuradio-source>/rfnoc-siggench2/rfnoc/Makefile.inc: RFNOC_SIGGEN2CH_DIR := $(OOT_DIR) include $(abspath $(RFNOC_SIGGEN2CH_DIR)/fpga-src/Makefile.inc) 2. <gnuradio-source>/rfnoc-siggench2/rfnoc/fpga-src/Makefile.inc: RFNOC_SRCS += $(addprefix $(RFNOC_SIGGEN2CH_DIR)/fpga-src/, \ noc_block_twochannelsiggen.v \ ) A side note, it's important to use "<something> := $(OOT_DIR)" to define a unique variable that represent the out-of-tree directory-- this reads the value of the OOT_DIR immediately, rather than deferring evaluation until later, a nagging "feature" of the make process. Of course, if you have no need of IP cores or HLS, you can happily delete all the Makefile.inc files in your repo and use the Makefile.srcs format that's supported via rfnocmodtool. Perhaps it's the easiest solution. EJ On Tue, Oct 3, 2017 at 4:52 PM, Nicolas Cuervo via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hello Jose, please try running the following: $ ./uhd_image_builder.py twochannelsiggen duc fft -I /home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/ -d x310 -t X310_RFNOC_HG -m 6 --fill-with-fifos which means pointing to the top OOT directory instead to directly the fpga-srcs directory. This small change was recently introduced and might be the source of your issue. I just modified the guide accordingly. Also, there is a possibility that you will face another path problem that has already been fixed, but is yet to be pushed into the repository. To avoid it, before running the uhd_image_builder, please go into the uhd_image_builder.py file and modify the L239 from: - curr_srcs = curr_srcs.replace('SOURCES_PATH', os.path.join(oot_path, 'rfnoc', 'fpga-src')) to: + curr_srcs = curr_srcs.replace('SOURCES_PATH', os.path.join(oot_path, 'rfnoc', 'fpga-src', '')) As said, this fix will be pushed soon, but for now you can avoid problems by doing it manually. Regards, - Nicolas On Tue, Oct 3, 2017 at 9:21 PM, Avila, Jose A via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: We are currently getting an error attempting to build a fpga image when running the following which points to the OOT module using the -I option ./uhd_image_builder.py twochannelsiggen duc fft -I /home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/fpga-src/ -d x310 -t X310_RFNOC_HG -m 6 --fill-with-fifos The testbench ran successfully but now the image builder is giving an error saying module noc_block_twochannelsiggen not found [.../top/x300/rfnoc_ce_auto_inst_x310.v] twochannelsiggen is the OOT module created with rfnocmodtool in the rfnoc-siggen2ch directory. We tried editing the Makefile.OOT.inc in /…/top/x300 with the following two lines OOT_DIR = /home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc include $(OOT_DIR)/Makefile.inc As well as editing the subsequent makefiles in the OOT rfnoc directory. We did notice that the Makefile.OOT.inc would get erased after running the image builder and it erroring out. The following is the error encountered with the image builder Parameter my_addr bound to: 237 - type: integer Parameter awidth bound to: 8 - type: integer Parameter width bound to: 32 - type: integer Parameter at_reset bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'setting_reg__parameterized18' (136#1) [/home/joseavila/Documents/gnuradio_source/fpga/usrp3/lib/control/setting_reg.v:12] INFO: [Synth 8-256] done synthesizing module 'rx_frontend_gen3' (137#1) [/home/joseavila/Documents/gnuradio_source/fpga/usrp3/lib/radio/rx_frontend_gen3.v:5] ERROR: [Synth 8-439] module 'noc_block_twochannelsiggen' not found [/home/joseavila/Documents/gnuradio_source/fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22] ERROR: [Synth 8-285] failed synthesizing module 'x300_core' [/home/joseavila/Documents/gnuradio_source/fpga/usrp3/top/x300/x300_core.v:2] ERROR: [Synth 8-285] failed synthesizing module 'x300' [/home/joseavila/Documents/gnuradio_source/fpga/usrp3/top/x300/x300.v:15] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:01:44 ; elapsed = 00:01:44 . Memory (MB): peak = 1351.676 ; gain = 517.594 ; free physical = 4123 ; free virtual = 14654 --------------------------------------------------------------------------------- RTL Elaboration failed INFO: [Common 17-83] Releasing license: Synthesis 552 Infos, 57 Warnings, 0 Critical Warnings and 4 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details INFO: [Common 17-206] Exiting Vivado at Mon Oct 2 15:23:15 2017... make[1]: *** [bin] Error 1 make[1]: Leaving directory `/home/joseavila/Documents/gnuradio_source/fpga/usrp3/top/x300' make: *** [X310_RFNOC_HG] Error 2 Thank you _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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