We are currently getting an error attempting to build a fpga image when running
the following which points to the OOT module using the -I option
./uhd_image_builder.py twochannelsiggen duc fft -I
/home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/fpga-src/ -d
x310 -t X310_RFNOC_HG -m 6 --fill-with-fifos
The testbench ran successfully but now the image builder is giving an error
saying module noc_block_twochannelsiggen not found
[.../top/x300/rfnoc_ce_auto_inst_x310.v]
twochannelsiggen is the OOT module created with rfnocmodtool in the
rfnoc-siggen2ch directory. We tried editing the Makefile.OOT.inc in
/…/top/x300 with the following two lines
OOT_DIR = /home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc
include $(OOT_DIR)/Makefile.inc
As well as editing the subsequent makefiles in the OOT rfnoc directory. We did
notice that the Makefile.OOT.inc would get erased after running the image
builder and it erroring out. The following is the error encountered with the
image builder
Parameter my_addr bound to: 237 - type: integer
Parameter awidth bound to: 8 - type: integer
Parameter width bound to: 32 - type: integer
Parameter at_reset bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'setting_reg__parameterized18'
(136#1)
[/home/joseavila/Documents/gnuradio_source/fpga/usrp3/lib/control/setting_reg.v:12]
INFO: [Synth 8-256] done synthesizing module 'rx_frontend_gen3' (137#1)
[/home/joseavila/Documents/gnuradio_source/fpga/usrp3/lib/radio/rx_frontend_gen3.v:5]
ERROR: [Synth 8-439] module 'noc_block_twochannelsiggen' not found
[/home/joseavila/Documents/gnuradio_source/fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22]
ERROR: [Synth 8-285] failed synthesizing module 'x300_core'
[/home/joseavila/Documents/gnuradio_source/fpga/usrp3/top/x300/x300_core.v:2]
ERROR: [Synth 8-285] failed synthesizing module 'x300'
[/home/joseavila/Documents/gnuradio_source/fpga/usrp3/top/x300/x300.v:15]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:01:44 ; elapsed = 00:01:44 .
Memory (MB): peak = 1351.676 ; gain = 517.594 ; free physical = 4123 ; free
virtual = 14654
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
552 Infos, 57 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console
or run log file for details
INFO: [Common 17-206] Exiting Vivado at Mon Oct 2 15:23:15 2017...
make[1]: *** [bin] Error 1
make[1]: Leaving directory
`/home/joseavila/Documents/gnuradio_source/fpga/usrp3/top/x300'
make: *** [X310_RFNOC_HG] Error 2
Thank you
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