For another customer I suggested adding a settings_reg (you'll find examples of that strewn all across the UHD code, if something's unclear, just ask) that would be a receiver for things like the clock divider's max counter value; these could be timed command-controlled.
Best regards, Marcus On 08/17/2017 05:33 PM, Martin Braun via USRP-users wrote: > Dan, > > you can also use timed commands to write to GPIOs at the "same time" as > a certain sample. I use quotes, because there's some delay between the > sample touching the radio state machine and it hitting the antenna, as > well as between GPIOs being toggled in the FPGA and the pin actually > going high or low. The actual values are hardware-dependent, and I don't > have any hard numbers here. However, they'll be deterministic (within a > small jitter). > > -- M > > On 08/17/2017 10:09 AM, Kuester, Dan (Fed) via USRP-users wrote: >> Marcus, >> >> >> >> Thanks for the guidance and detail! >> >> >> >> The fastest clock frequencies I’m looking for would probably run on the >> order of ~1 kHz – 100 kHz, but being able to tie it to the sample clock >> would be key for my application (sort of a self-calibrating radiometer). >> >> >> >> I’ll start with a look gpio_atr_io.v, it does sound promising. I may try >> to coopt the GPIO/ATR messages exposed through the UHD API to configure >> the counter and polarity. >> >> >> >> Dan >> >> >> >> *From:*USRP-users [mailto:usrp-users-boun...@lists.ettus.com] *On Behalf >> Of *Marcus Müller via USRP-users >> *Sent:* Thursday, August 17, 2017 7:40 AM >> *To:* usrp-users@lists.ettus.com >> *Subject:* Re: [USRP-users] clock outputs to GPIO? >> >> >> >> Hi Dan, >> >> what's the order of frequency of the clock you're trying to drive? >> >> Three thoughts: >> >> * I agree, for anything beyond let's say 1kHz (don't nail me on this), >> using timed commands from the host to control the exact GPIO >> transition would only work in theory, but not in practice, since the >> command queues will quickly fill up >> * The front panel GPIO connector is ESD-protected, and those diodes do >> have a non-negligible capacitance. That will become a problem pretty >> quickly after a couple of MHz >> * Technically, not that hard; modify gpio_atr_io.v to include a >> counter instead of direct register output for one of the outputs :) >> >> Best regards, >> Marcus >> >> >> >> On 08/16/2017 09:56 PM, Kuester, Dan (Fed) via USRP-users wrote: >> >> Hello everyone, >> >> >> >> I’m looking for a way to drive the GPIO outputs on my x310 with a >> clock output divided down from the sample clock (or multiplied up >> from 1 PPS), which I would use to drive an external switch. >> >> >> >> I’m hoping for tight, deterministic timing, so I’m skeptical of >> manual API calls routed through the host for each clock transition. >> I don’t see support for other options in the UHD GPIO API >> documentation, so I’m guessing I’d need to do this with custom FPGA >> logic (though please correct me if I’m wrong!). >> >> >> >> Is anyone aware of any literature or example projects that have >> implemented something like this? >> >> >> >> Thanks! >> >> >> >> Dan >> >> >> >> >> _______________________________________________ >> >> USRP-users mailing list >> >> USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com> >> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >> >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
