Hi Dan,
what's the order of frequency of the clock you're trying to drive?
Three thoughts:
* I agree, for anything beyond let's say 1kHz (don't nail me on this),
using timed commands from the host to control the exact GPIO
transition would only work in theory, but not in practice, since the
command queues will quickly fill up
* The front panel GPIO connector is ESD-protected, and those diodes do
have a non-negligible capacitance. That will become a problem pretty
quickly after a couple of MHz
* Technically, not that hard; modify gpio_atr_io.v to include a
counter instead of direct register output for one of the outputs :)
Best regards,
Marcus
On 08/16/2017 09:56 PM, Kuester, Dan (Fed) via USRP-users wrote:
>
> Hello everyone,
>
>
>
> I’m looking for a way to drive the GPIO outputs on my x310 with a
> clock output divided down from the sample clock (or multiplied up from
> 1 PPS), which I would use to drive an external switch.
>
>
>
> I’m hoping for tight, deterministic timing, so I’m skeptical of manual
> API calls routed through the host for each clock transition. I don’t
> see support for other options in the UHD GPIO API documentation, so
> I’m guessing I’d need to do this with custom FPGA logic (though please
> correct me if I’m wrong!).
>
>
>
> Is anyone aware of any literature or example projects that have
> implemented something like this?
>
>
>
> Thanks!
>
>
>
> Dan
>
>
>
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