On Fri, Feb 17, 2012 at 05:35:20PM +0530, R Sricharan wrote: > The OMAP5 silicon has new DDR PHY design, which includes a external PHY > as well. So configuring the ext PHY parameters here. Also the EMIF timimg > registers and a couple of DDR mode registers needs to be updated based on > the testing from the actual silicon. [snip] > + /* external phy 6-24 registers do not change with > + * ddr frequency
Here and elsewhere, incorrectly styled comments. [snip] > /* Maximum delay before Low Power Modes */ > +#ifndef CONFIG_OMAP54XX > #define REG_CS_TIM 0xF > +#else > +#define REG_CS_TIM 0x0 > +#endif You used spaces not tabs and I think checkpatch will note that for you as well (so I expect v2 of the series to be checkpatch clean, aside from 80char wide stuff in those tables). -- Tom _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
