The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.
Signed-off-by: R Sricharan <r.sricha...@ti.com>
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 15 +++--------
arch/arm/cpu/armv7/omap4/clocks.c | 15 +++++++++++
arch/arm/cpu/armv7/omap5/clocks.c | 31 +++++++++++++++++-------
arch/arm/include/asm/arch-omap4/clocks.h | 1 +
arch/arm/include/asm/arch-omap5/clocks.h | 16 ++++++++----
5 files changed, 53 insertions(+), 25 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 5e30cd4..1a0328f 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -390,23 +390,16 @@ void do_scale_tps62361(u32 reg, u32 volt_mv)
void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
{
u32 temp, offset_code;
- u32 step = 12660; /* 12.66 mV represented in uV */
+
u32 offset = volt_mv;
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
- if (omap_revision() == OMAP4430_ES1_0)
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
- else
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
- offset_code = (offset + step - 1) / step;
- /* The code starts at 1 not 0 */
- offset_code++;
+ offset_code = get_offset_code(offset);
- debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
- offset_code);
+ debug("do_scale_vcore: vcore_reg - 0x%x volt - %d offset_code - 0x%x\n",
+ vcore_reg, volt_mv, offset_code);
temp = SMPS_I2C_SLAVE_ADDR |
(vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c
b/arch/arm/cpu/armv7/omap4/clocks.c
index e2189f7..98e179d 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -318,6 +318,21 @@ void scale_vcores(void)
}
}
+u32 get_offset_code(u32 offset)
+{
+ u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
+
+ if (omap_revision() == OMAP4430_ES1_0)
+ offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+ else
+ offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+ offset_code = (offset + step - 1) / step;
+
+ /* The code starts at 1 not 0 */
+ return ++offset_code;
+}
+
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c
b/arch/arm/cpu/armv7/omap5/clocks.c
index b2768a4..71916c1 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -264,17 +264,30 @@ void scale_vcores(void)
setup_sri2c();
- /* Enable 1.22V from TPS for vdd_mpu */
- volt = 1220;
- do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
+ /* Palmas settings */
+ volt = VDD_MPU;
+ do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
- /* VCORE 1 - for vdd_core */
- volt = 1000;
- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+ volt = VDD_MM;
+ do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
- /* VCORE 2 - for vdd_MM */
- volt = 1125;
- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+ volt = VDD_CORE;
+ do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
+}
+
+u32 get_offset_code(u32 volt_offset)
+{
+ u32 offset_code, step = 10000; /* 10 mV represented in uV */
+
+ volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
+
+ offset_code = (volt_offset + step - 1) / step;
+
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ return offset_code + 6;
}
/*
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h
b/arch/arm/include/asm/arch-omap4/clocks.h
index cd304e8..e52595b 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -754,6 +754,7 @@ extern struct omap4_prcm_regs *const prcm;
extern const u32 sys_clk_array[8];
void scale_vcores(void);
+u32 get_offset_code(u32 offset);
void do_scale_tps62361(u32 reg, u32 volt_mv);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h
b/arch/arm/include/asm/arch-omap5/clocks.h
index faed887..b36638e 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -647,12 +647,17 @@ struct omap5_prcm_regs {
/* SMPS */
#define SMPS_I2C_SLAVE_ADDR 0x12
-#define SMPS_REG_ADDR_VCORE1 0x55
-#define SMPS_REG_ADDR_VCORE2 0x5B
-#define SMPS_REG_ADDR_VCORE3 0x61
+#define SMPS_REG_ADDR_12_MPU 0x23
+#define SMPS_REG_ADDR_45_IVA 0x2B
+#define SMPS_REG_ADDR_8_CORE 0x37
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
+/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
+#define VDD_MPU 1000
+#define VDD_MM 1000
+#define VDD_CORE 1040
+
+/* Standard offset is 0.5v expressed in uv */
+#define PALMAS_SMPS_BASE_VOLT_UV 500000
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
@@ -713,6 +718,7 @@ extern struct omap5_prcm_regs *const prcm;
extern const u32 sys_clk_array[8];
void scale_vcores(void);
+u32 get_offset_code(u32 offset);
void do_scale_tps62361(u32 reg, u32 volt_mv);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
--
1.7.1
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