On Fri, Nov 25, 2011 at 9:44 AM, Marek Vasut <marek.va...@gmail.com> wrote: >> This handler can be activated on multi-processor systems to boot only >> the master CPU. All slave CPUs are halted by executing the WAIT >> instruction. This is also useful to reduce the power consumption at >> boot time. >> >> Signed-off-by: Daniel Schwierzeck <daniel.schwierz...@googlemail.com> >> --- >> arch/mips/cpu/mips32/start.S | 16 ++++++++++++++++ >> 1 files changed, 16 insertions(+), 0 deletions(-) >> >> diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S >> index 9c1b2f7..b6cb4be 100644 >> --- a/arch/mips/cpu/mips32/start.S >> +++ b/arch/mips/cpu/mips32/start.S >> @@ -224,6 +224,14 @@ reset: >> >> setup_c0_status_reset >> >> + /* Set all slave CPUs in sleep mode */ >> +#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP >> + mfc0 k0, CP0_EBASE >> + and k0, EBASEF_CPUNUM >> + bne k0, zero, slave_cpu_sleep >> + nop >> +#endif >> + >> /* Init Timer */ >> mtc0 zero, CP0_COUNT >> mtc0 zero, CP0_COMPARE >> @@ -383,3 +391,11 @@ romReserved: >> >> romExcHandle: >> b romExcHandle >> + >> + /* Additional handlers */ >> +#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP >> +slave_cpu_sleep: >> + wait >> + b slave_cpu_sleep >> + nop >> +#endif > > Can't you stall the CPU instead of letting it run in an empty loop? If not: > > Acked-by: Marek Vasut <marek.va...@gmail.com> >
the CPU is stalled with the wait instruction. The loop is actually paranoia ;) From MIPS32 24KE Processor Core Family Software User's Manual: The WAIT instruction forces the core into low power mode. The pipeline is stalled and when all external requests are completed, the processor’s main clock is stopped. The processor will restart when reset (SI_Reset) is signaled, or a non-masked interrupt is taken (SI_NMI, SI_Int, or EJ_DINT). Note that the core does not use the code field in this instruction. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
