On Nov 10, 2011, at 3:11 PM, Ira W. Snyder wrote:
> This adds support for the Freescale COM Express P2020 board. This board
> is similar to the P1_P2_RDB, but has some extra (as well as missing)
> peripherals.
>
> Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
> Using the HRESET_REQ register does not work.
>
> This board has no NOR flash, and can only be booted via SD or SPI. This
> procedure is documented in Freescale Document Number AN3659 "Booting
> from On-Chip RAM (eSDHC or eSPI)." Some alternative documentation is
> provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
> Processor Reference Manual" (section 4.5).
>
> Signed-off-by: Ira W. Snyder <i...@ovro.caltech.edu>
> ---
>
> diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
> new file mode 100644
> index 0000000..dd2a4dd
> --- /dev/null
> +++ b/board/freescale/p2020come/ddr.c
> @@ -0,0 +1,245 @@
> +/*
> + * Copyright 2009, 2011 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/mmu.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/processor.h>
> +#include <asm/fsl_ddr_sdram.h>
> +#include <asm/io.h>
> +#include <asm/fsl_law.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
> +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
> +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
> +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
> +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
> +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
> +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
> +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
> +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
> +#define CONFIG_SYS_DDR_RCW_1 0x00000000
> +#define CONFIG_SYS_DDR_RCW_2 0x00000000
> +#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
> +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
> +#define CONFIG_SYS_DDR_TIMING_4 0x00000000
> +#define CONFIG_SYS_DDR_TIMING_5 0x00000000
> +
> +#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
> +#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
> +#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
> +#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
> +#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
> +#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
> +
> +#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
> +#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
> +#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
> +#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
> +#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
> +#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
> +
> +#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
> +#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
> +#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
> +#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
> +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
> +#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
> +#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
> +
> +#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
> +#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
> +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
> +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
> +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
> +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
> + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
> + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
> + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
> + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
> + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
> + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
> + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
> + .ddr_data_init = CONFIG_MEM_INIT_VALUE,
> + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
> + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> +};
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
> + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
> + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
> + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
> + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
> + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
> + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
> + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
> + .ddr_data_init = CONFIG_MEM_INIT_VALUE,
> + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
> + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> +};
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
> + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
> + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
> + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
> + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
> + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
> + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
> + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
> + .ddr_data_init = CONFIG_MEM_INIT_VALUE,
> + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
> + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> +};
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
> + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
> + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
> + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
> + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
> + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
> + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
> + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
> + .ddr_data_init = CONFIG_MEM_INIT_VALUE,
> + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
> + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> +};
> +
> +/*
> + * Fixed sdram init -- doesn't use serial presence detect.
> + */
> +
> +phys_size_t fixed_sdram(void)
> +{
> + char buf[32];
> + fsl_ddr_cfg_regs_t ddr_cfg_regs;
> + size_t ddr_size;
> + struct cpu_type *cpu;
> + ulong ddr_freq, ddr_freq_mhz;
> +
> + cpu = gd->cpu;
> + /* P1020 and it's derivatives support max 32bit DDR width */
> + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
> + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
> + ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
These checks don't make sense if you are a P2020 SoC
> + } else {
> + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
> + }
> +#if defined(CONFIG_SYS_RAMBOOT)
> + return ddr_size;
> +#endif
> + ddr_freq = get_ddr_freq(0);
> + ddr_freq_mhz = ddr_freq / 1000000;
> +
> + printf("Configuring DDR for %s MT/s data rate\n",
> + strmhz(buf, ddr_freq));
> +
> + if (ddr_freq_mhz <= 400)
> + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
> + else if (ddr_freq_mhz <= 533)
> + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
> + else if (ddr_freq_mhz <= 667)
> + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
> + else if (ddr_freq_mhz <= 800)
> + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
> + else
> + panic("Unsupported DDR data rate %s MT/s data rate\n",
> + strmhz(buf, ddr_freq));
Does the board really support different DDR freq or is this copy / paste?
> +
> + /* P1020 and it's derivatives support max 32bit DDR width */
> + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
> + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
> + ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
> + ddr_cfg_regs.cs[0].bnds = 0x0000001F;
> + }
Same comment as above
> +
> + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
> +
> + set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
> + return ddr_size;
> +}
> diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
> new file mode 100644
> index 0000000..56508db
> --- /dev/null
> +++ b/board/freescale/p2020come/law.c
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/fsl_law.h>
> +#include <asm/mmu.h>
> +
> +struct law_entry law_table[] = {
> + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
> + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
> + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
> + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
> + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
> + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
We normally set these up dynamically.
> +};
> +
> +int num_law_entries = ARRAY_SIZE(law_table);
> diff --git a/board/freescale/p2020come/p2020come.c
> b/board/freescale/p2020come/p2020come.c
> new file mode 100644
> index 0000000..2e334cf
> --- /dev/null
> +++ b/board/freescale/p2020come/p2020come.c
> @@ -0,0 +1,401 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <hwconfig.h>
> +#include <command.h>
> +#include <asm/processor.h>
> +#include <asm/mmu.h>
> +#include <asm/cache.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/fsl_serdes.h>
> +#include <asm/io.h>
> +#include <miiphy.h>
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +#include <fsl_mdio.h>
> +#include <tsec.h>
> +#include <vsc7385.h>
> +#include <netdev.h>
> +#include <mmc.h>
> +#include <malloc.h>
> +#include <i2c.h>
> +
> +#if defined(CONFIG_PCI)
> +#include <asm/fsl_pci.h>
> +#include <pci.h>
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if defined(CONFIG_PCI)
> +void pci_init_board(void)
> +{
> + fsl_pcie_init_board(0);
> +}
> +
> +void ft_pci_board_setup(void *blob)
> +{
> + FT_FSL_PCI_SETUP;
> +}
> +#endif
> +
> +/*
> + * GPIO
> + * 0 - 3: CarryBoard Input;
> + * 4 - 7: CarryBoard Output;
> + * 8 : Mux as SDHC_CD (card detection)
> + * 9 : Mux as SDHC_WP
> + * 10 : Clear Watchdog timer
> + * 11 : LED Input
> + * 12 : Output to 1
> + * 13 : Open Drain
> + * 14 : LED Output
> + * 15 : Switch Input
> + */
> +#define GPIO_DIR 0x0f3a0000
> +#define GPIO_ODR 0x00000000
> +
> +#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
> + SGMII_PHY_RST_SET | PCIE_RST_SET | \
> + RGMII_PHY_RST_SET)
> +
> +#define SYSCLK_MASK 0x00200000
> +#define BOARDREV_MASK 0x10100000
> +#define BOARDREV_B 0x10100000
> +#define BOARDREV_C 0x00100000
> +#define BOARDREV_D 0x00000000
> +
> +#define SYSCLK_66 66666666
> +#define SYSCLK_50 50000000
> +#define SYSCLK_100 100000000
> +
> +unsigned long get_board_sys_clk(ulong dummy)
> +{
> + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> + u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
> +
> + ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> + switch (ddr_ratio) {
> + case 0x0C:
> + return SYSCLK_66;
> + case 0x0A:
> + case 0x08:
> + return SYSCLK_100;
> + default:
> + puts("ERROR: unknown DDR ratio\n");
> + return SYSCLK_100;
> + }
> +}
> +
> +unsigned long get_board_ddr_clk(ulong dummy)
> +{
> + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> + u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
> +
> + ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> + switch (ddr_ratio) {
> + case 0x0C:
> + case 0x0A:
> + return SYSCLK_66;
> + case 0x08:
> + return SYSCLK_100;
> + default:
> + puts("ERROR: unknown DDR ratio\n");
> + return SYSCLK_100;
> + }
> +}
> +
> +#ifdef CONFIG_MMC
> +int board_early_init_f(void)
> +{
> + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +
> + setbits_be32(&gur->pmuxcr,
> + (MPC85xx_PMUXCR_SDHC_CD |
> + MPC85xx_PMUXCR_SDHC_WP));
> +
> + /* All the device are enable except for SRIO12 */
> + setbits_be32(&gur->devdisr, 0x80000);
Add a #define instead of magic 0x80000
> + return 0;
> +}
> +#endif
> +
> +int checkboard(void)
> +{
> + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
> +
> + /*
> + * GPIO
> + * 0 - 3: CarryBoard Input;
> + * 4 - 7: CarryBoard Output;
> + * 8 : Mux as SDHC_CD (card detection)
> + * 9 : Mux as SDHC_WP
> + * 10 : Clear Watchdog timer
> + * 11 : LED Input
> + * 12 : Output to 1
> + * 13 : Open Drain
> + * 14 : LED Output
> + * 15 : Switch Input
> + *
> + * Set GPIOs 11, 12, 14 to 1.
> + */
> + out_be32(&pgpio->gpdir, GPIO_DIR);
> + out_be32(&pgpio->gpodr, GPIO_ODR);
> + out_be32(&pgpio->gpdat, 0x001A0000);
look at using mpc85xx_gpio.h
> +
> + puts("Board: Freescale COM Express P2020\n");
> + return 0;
> +}
> +
> +#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
> +
> +static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
> +{
> + u8 data;
> +
> + if (i2c_read(0x68, reg, 1, &data, 1)) {
> + M41ST85W_ERROR("unable to read %s bit\n", name);
> + return;
> + }
> +
> + if (data & mask) {
> + data &= ~mask;
> + if (i2c_write(0x68, reg, 1, &data, 1)) {
> + M41ST85W_ERROR("unable to clear %s bit\n", name);
> + return;
> + }
> + }
> +}
> +
> +/*
> + * The P2020COME board has a STMicro M41ST85W RTC/watchdog
> + * at i2c bus 1 address 0x68.
> + */
> +static void start_rtc(void)
> +{
> + unsigned int bus = i2c_get_bus_num();
> +
> + if (i2c_set_bus_num(1)) {
> + M41ST85W_ERROR("unable to set i2c bus\n");
> + goto out;
> + }
> +
> + /* ensure ST (stop) and HT (halt update) bits are cleared */
> + m41st85w_clear_bit(0x1, 0x80, "ST");
> + m41st85w_clear_bit(0xc, 0x40, "HT");
> +
> +out:
> + /* reset the i2c bus */
> + i2c_set_bus_num(bus);
> +}
> +
> +int board_early_init_r(void)
> +{
> + start_rtc();
> + return 0;
> +}
> +
> +void board_reset(void)
> +{
> + u8 data = (1 << 2) | 0x82;
some #defines instead of magic #s
> +
> + /* set the hardware watchdog timeout to 1 second, then hang */
> + i2c_set_bus_num(1);
> + i2c_write(0x68, 9, 1, &data, 1);
> +
> + while (1)
> + /* hang */;
> +}
> +
> +#ifdef CONFIG_TSEC_ENET
> +int board_eth_init(bd_t *bis)
> +{
> + struct fsl_pq_mdio_info mdio_info;
> + struct tsec_info_struct tsec_info[4];
> + int num = 0;
> +
> +#ifdef CONFIG_TSEC1
> + SET_STD_TSEC_INFO(tsec_info[num], 1);
> + num++;
> +#endif
> +#ifdef CONFIG_TSEC2
> + SET_STD_TSEC_INFO(tsec_info[num], 2);
> + num++;
> +#endif
> +#ifdef CONFIG_TSEC3
> + SET_STD_TSEC_INFO(tsec_info[num], 3);
> + if (is_serdes_configured(SGMII_TSEC3)) {
> + puts("eTSEC3 is in sgmii mode.");
> + tsec_info[num].flags |= TSEC_SGMII;
> + }
> + num++;
> +#endif
> + if (!num) {
> + printf("No TSECs initialized\n");
> + return 0;
> + }
> +
> + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
> + mdio_info.name = DEFAULT_MII_NAME;
> + fsl_pq_mdio_init(bis, &mdio_info);
> +
> + tsec_eth_init(bis, tsec_info, num);
> +
> + return pci_eth_init(bis);
> +}
> +#endif
> +
> +#if defined(CONFIG_OF_BOARD_SETUP)
> +void fdt_fixup_add_2nd_usb(void *blob, int agent)
> +{
What are you trying to do here?
> + const char *soc_compat = "fsl,p2020-immr";
> + const char *lbc_compat = "fsl,p2020-elbc";
> + const u32 *addrcell, *sizecell, *ph;
> + int off, lbcoff, len, err;
> + u32 *regbuf = NULL;
> + u32 *irqbuf = NULL;
> +
> + off = fdt_node_offset_by_compatible(blob, -1, soc_compat);
> + if (off < 0) {
> + printf("WARNING: could not find compatible node %s: %s.\n",
> + soc_compat, fdt_strerror(off));
> + return;
> + }
> +
> + lbcoff = fdt_node_offset_by_compatible(blob, -1, lbc_compat);
> + if (lbcoff < 0) {
> + printf("WARNING: could not find compatible node %s: %s.\n",
> + lbc_compat, fdt_strerror(lbcoff));
> + return;
> + }
> +
> + addrcell = fdt_getprop(blob, off, "#address-cells", NULL);
> + sizecell = fdt_getprop(blob, off, "#size-cells", NULL);
> +
> + off = fdt_add_subnode(blob, off, "usb@23000");
> + if (off < 0) {
> + printf("WARNING: could not add 2nd usb node %s.\n",
> + fdt_strerror(off));
> + return;
> + }
> +
> + err = fdt_setprop_cell(blob, off, "#address-cells", 1);
> + if (err < 0)
> + printf("WARNING: could not set #address-cell property: %s\n",
> + fdt_strerror(err));
> +
> + err = fdt_setprop_cell(blob, off, "#size-cells", 0);
> + if (err < 0)
> + printf("WARNING: could not set #size-cells property: %s\n",
> + fdt_strerror(err));
> +
> + err = fdt_setprop_string(blob, off, "compatible", "fsl-usb2-dr");
> + if (err < 0)
> + printf("WARNING: could not set compatible property: %s\n",
> + fdt_strerror(err));
> +
> + err = fdt_setprop_string(blob, off, "phy_type", "ulpi");
> + if (err < 0)
> + printf("WARNING: could not set phy_type property: %s\n",
> + fdt_strerror(err));
> +
> + if (agent) {
> + err = fdt_setprop_string(blob, off, "dr_mode", "peripheral");
> + if (err < 0)
> + printf("WARNING: could not set dr_mode property: %s\n",
> + fdt_strerror(err));
> + }
> +
> + if (addrcell && *addrcell == 2) {
> + regbuf[0] = 0;
> + regbuf[1] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
> + len = 2;
> + } else {
> + regbuf[0] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
> + len = 1;
> + }
> +
> + if (sizecell && *sizecell == 2) {
> + regbuf[len] = 0;
> + regbuf[len + 1] = 0x1000;
> + len = 2;
> + } else {
> + regbuf[len] = 0x1000;
> + len++;
> + }
> +
> + err = fdt_setprop(blob, off, "reg", regbuf, len * sizeof(u32));
> + if (err < 0)
> + printf("WARNING: could not set <%s> %s\n",
> + "reg", fdt_strerror(err));
> +
> + irqbuf[0] = 0x2e;
> + irqbuf[1] = 0x2;
> +
> + err = fdt_setprop(blob, off, "interrupts", irqbuf, 2 * sizeof(u32));
> + if (err < 0)
> + printf("WARNING: could not set %s %s\n",
> + "interrupts", fdt_strerror(err));
> +
> + ph = fdt_getprop(blob, lbcoff, "interrupt-parent", 0);
> + if (!ph) {
> + printf("WARNING: could not read interrupt-parent property\n");
> + return;
> + }
> +
> + err = fdt_setprop(blob, off, "interrupt-parent", ph, sizeof(u32));
> + if (err < 0)
> + printf("WARNING: could not set %s %s\n",
> + "interrupt-parent", fdt_strerror(err));
> +}
> +
> +void ft_board_setup(void *blob, bd_t *bd)
> +{
> + phys_addr_t base;
> + phys_size_t size;
> + int agent;
> +
> + ft_cpu_setup(blob, bd);
> +
> + base = getenv_bootm_low();
> + size = getenv_bootm_size();
> +
> +#if defined(CONFIG_PCI)
> + ft_pci_board_setup(blob);
> +#endif
> +
> + fdt_fixup_memory(blob, (u64)base, (u64)size);
> +
> + if (!hwconfig("usb2"))
> + return;
> +
> + agent = hwconfig_subarg_cmp("usb2", "dr_mode", "peripheral");
> +
> + /*
> + * Add the 2nd usb node and enable it. eLBC will
> + * now be disabled since it is MUXed with USB2
> + */
> +
> + fdt_fixup_add_2nd_usb(blob, agent);
> +}
> +#endif
> diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
> new file mode 100644
> index 0000000..e1dd056
> --- /dev/null
> +++ b/board/freescale/p2020come/tlb.c
> @@ -0,0 +1,100 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/mmu.h>
> +
For any regions that do NOT have code, we should remove MAS3_SX bit:
> +struct fsl_e_tlb_entry tlb_table[] = {
> + /* TLB 0 - for temp stack in cache */
> + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
> + CONFIG_SYS_INIT_RAM_ADDR_PHYS,
> + MAS3_SX|MAS3_SW|MAS3_SR, 0,
> + 0, 0, BOOKE_PAGESZ_4K, 0),
> + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
> + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
> + MAS3_SX|MAS3_SW|MAS3_SR, 0,
> + 0, 0, BOOKE_PAGESZ_4K, 0),
> + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
> + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
> + MAS3_SX|MAS3_SW|MAS3_SR, 0,
> + 0, 0, BOOKE_PAGESZ_4K, 0),
> + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
> + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
> + MAS3_SX|MAS3_SW|MAS3_SR, 0,
> + 0, 0, BOOKE_PAGESZ_4K, 0),
> +
> + /* TLB 1 */
> + /* *I*** - Covers boot page */
> + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 0, BOOKE_PAGESZ_4K, 1),
> +
> + /* *I*G* - CCSRBAR */
> + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 1, BOOKE_PAGESZ_1M, 1),
> +
> +#if defined(CONFIG_PCI)
> + /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
> + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 2, BOOKE_PAGESZ_1G, 1),
> +
> + /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
> + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 3, BOOKE_PAGESZ_256M, 1),
> +
> +
> + /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
> + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
> + CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 4, BOOKE_PAGESZ_256M, 1),
> +
> + /*
> + * *I*G* - PCI I/O
> + *
> + * PCI3 => 0xFFC10000
> + * PCI2 => 0xFFC2,0000
> + * PCI1 => 0xFFC3,0000
> + */
> + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 5, BOOKE_PAGESZ_256K, 1),
> +#endif /* #if defined(CONFIG_PCI) */
> +
> +#if defined(CONFIG_SYS_RAMBOOT)
> + /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
> + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 6, BOOKE_PAGESZ_1G, 1),
> +
> + /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
> + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
> + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 7, BOOKE_PAGESZ_1G, 1),
> +#endif
> +};
> +
> +int num_tlb_entries = ARRAY_SIZE(tlb_table);
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