Adding York who might be able to help more... -M
On Fri, Nov 11, 2011 at 4:18 PM, Ira W. Snyder <i...@ovro.caltech.edu> wrote: > On Fri, Nov 11, 2011 at 09:07:23PM +0000, McClintock Matthew-B29882 wrote: >> On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder <i...@ovro.caltech.edu> wrote: >> > Thanks. That config_sram.dat is exactly what I came up with. >> > >> > I have my board booting via L2SRAM, but the DDR doesn't get configured >> > correctly yet. I'm trying to figure out how the DDR SPD stuff works in >> > U-Boot. I've never used it before. I'm following the P2020DS code as an >> > example, but I haven't yet figured out how the code in >> > board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters >> > structure especially). >> >> If you board has i2c to the ddr modules it should be able to use the >> timing info from there. I think CONFIG_DDR_SPD is the config option >> you are looking for. I know the P2020DS does SPD from L2SRAM. >> > > The only thing that looks like an SPD chip is at i2c bus 1, address > 0x53. I setup my board configuration with: > > #define CONFIG_FSL_DDR3 > #define CONFIG_FSL_DDR_INTERACTIVE > #define CONFIG_CHIP_SELECTS_PER_CTRL 2 > #define CONFIG_SYS_DDR_SBE 0x00010000 > > #define CONFIG_DDR_SPD > #define CONFIG_SYS_SPD_BUS_NUM 1 > #define SPD_EEPROM_ADDRESS 0x53 > > Some of the settings the SPD code computes are correct, and some are > completely wrong. I can't figure out how to make this work. > > Here is the raw SPD dumped from a working U-Boot: > > 0000: 92 10 0b 08 02 11 00 09 0b 52 01 08 0c 00 3e 00 .........R....>. > 0010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 05 ixi0i. .p.<<.... > 0020: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 1f 00 ................ > 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 0070: 00 00 00 00 00 01 94 01 10 25 03 ae 48 48 e3 e3 .........%..HH.. > 0080: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32 SG572568EMR069S2 > 0090: 53 46 00 00 80 ce 53 4d 41 52 54 4d 6f 64 75 6c SF....SMARTModul > 00a0: 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00 arTechnologies.. > 00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > > And here is the output of an interactive FSL DDR run: > > U-Boot 2011.09-00929-g3b5f71c-dirty (Nov 11 2011 - 13:31:13) > > CPU0: P2020E, Version: 2.0, (0x80ea0020) > Core: E500, Version: 5.0, (0x80211050) > Clock Configuration: > CPU0:1200 MHz, CPU1:1200 MHz, > CCB:600 MHz, > DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500 MHz > L1: D-cache 32 kB enabled > I-cache 32 kB enabled > Board: Freescale COM Express P2020 > I2C: ready > SPI: ready > DRAM: FSL DDR> > FSL DDR> > FSL DDR>compute > unknown module_type 0x08 > Detected UDIMM SG572568EMR069S2SF > The choosen cas latency 16 is too large > FSL DDR>print c0 d0 > SPD info: Controller=0 DIMM=0 > 0 : 92 info_size_crc bytes written into serial memory, CRC coverage > 1 : 10 spd_rev SPD Revision > 2 : 0b mem_type Key Byte / DRAM Device Type > 3 : 08 module_type Key Byte / Module Type > 4 : 02 density_banks SDRAM Density and Banks > 5 : 11 addressing SDRAM Addressing > 6 : 00 module_vdd Module Nominal Voltage, VDD > 7 : 09 organization Module Organization > 8 : 0b bus_width Module Memory Bus Width > 9 : 52 ftb_div Fine Timebase (FTB) Dividend / Divisor > 10 : 01 mtb_dividend Medium Timebase (MTB) Dividend > 11 : 08 mtb_divisor Medium Timebase (MTB) Divisor > 12 : 0c tCK_min SDRAM Minimum Cycle Time > 13 : 00 res_13 Reserved > 14 : 3e caslat_lsb CAS Latencies Supported, LSB > 15 : 00 caslat_msb CAS Latencies Supported, MSB > 16 : 69 tAA_min Min CAS Latency Time > 17 : 78 tWR_min Min Write REcovery Time > 18 : 69 tRCD_min Min RAS# to CAS# Delay Time > 19 : 30 tRRD_min Min Row Active to Row Active Delay Time > 20 : 69 tRP_min Min Row Precharge Delay Time > 21 : 11 tRAS_tRC_ext Upper Nibbles for tRAS and tRC > 22 : 20 tRAS_min_lsb Min Active to Precharge Delay Time, LSB > 23 : 89 tRC_min_lsb Min Active to Active/Refresh Delay Time, LSB > 24 : 70 tRFC_min_lsb Min Refresh Recovery Delay Time LSB > 25 : 03 tRFC_min_msb Min Refresh Recovery Delay Time MSB > 26 : 3c tWTR_min Min Internal Write to Read Command Delay Time > 27 : 3c tRTP_min Min Internal Read to Precharge Command Delay Time > 28 : 00 tFAW_msb Upper Nibble for tFAW > 29 : f0 tFAW_min Min Four Activate Window Delay Time > 30 : 83 opt_features SDRAM Optional Features > 31 : 05 therm_ref_opt SDRAM Thermal and Refresh Opts > 32 : 80 therm_sensor SDRAM Thermal Sensor > 33 : 00 device_type SDRAM Device Type > 34 - 59: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 > 60 -116: > 0f111f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000117 > : 01 Module MfgID Code LSB - JEP-106 > 118 : 94 Module MfgID Code MSB - JEP-106 > 119 : 01 Mfg Location > 120-121: 10 25 Mfg Date > 122-125: 03 ae 48 48 Module Serial Number > 126-127: e3 e3 SPD CRC > 128-145: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32 53 46 Mfg's > Module Part Number > 146-147: 00 00 Module Revision code > 148 : 80 DRAM MfgID Code LSB - JEP-106 > 149 : ce DRAM MfgID Code MSB - JEP-106 > 150-175: 53 4d 41 52 54 4d 6f 64 75 6c 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 > 73 00 00 Mfg's Specific Data > 176-255: > 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 > Mfg's Specific Data > > > > DIMM parameters: Controller=0 DIMM=0 > DIMM organization parameters: > module part name = SG572568EMR069S2SF > rank_density = 1073741824 bytes (1024 megabytes) > capacity = 2147483648 bytes (2048 megabytes) > burst_lengths_bitmask = 00 > base_addresss = 0 (00000000 00000000) > n_ranks = 2 > data_width = 72 > primary_sdram_width = 64 > ec_sdram_width = 8 > registered_dimm = 0 > n_row_addr = 0 > n_col_addr = 0 > edc_config = 0 > n_banks_per_sdram_device = 0 > tCKmin_X_ps = 0 > tCKmin_X_minus_1_ps = 0 > tCKmin_X_minus_2_ps = 0 > tCKmax_ps = 0 > caslat_X = 0 > tAA_ps = 0 > caslat_X_minus_1 = 0 > caslat_X_minus_2 = 0 > caslat_lowest_derated = 0 > tRCD_ps = 0 > tRP_ps = 0 > tRAS_ps = 0 > tWR_ps = 0 > tWTR_ps = 0 > tRFC_ps = 0 > tRRD_ps = 0 > tRC_ps = 0 > refresh_rate_ps = 0 > tIS_ps = 0 > tIH_ps = 0 > tDS_ps = 0 > tDH_ps = 0 > tRTP_ps = 0 > tDQSQ_max_ps = 0 > tQHS_ps = 0 > > > > "lowest common" DIMM parameters: Controller=0 > tCKmin_X_ps = 0 (4294967295 MHz) > tCKmax_ps = 0 (4294967295 MHz) > all_DIMMs_burst_lengths_bitmask = 00 > tCKmax_max_ps = 0 > tRCD_ps = 0 > tRP_ps = 0 > tRAS_ps = 0 > tWR_ps = 0 > tWTR_ps = 0 > tRFC_ps = 0 > tRRD_ps = 0 > tRC_ps = 0 > refresh_rate_ps = 0 > tIS_ps = 0 > tDS_ps = 0 > tDH_ps = 0 > tRTP_ps = 0 > tDQSQ_max_ps = 0 > tQHS_ps = 0 > lowest_common_SPD_caslat = 0 > highest_common_derated_caslat = 0 > additive_latency = 0 > ndimms_present = 1 > all_DIMMs_registered = 0 > all_DIMMs_unbuffered = 1 > all_DIMMs_ECC_capable = 0 > total_mem = 2147483648 (2048 megabytes) > base_address = 0 (0 megabytes) > > > User Config Options: Controller=0 > cs0_odt_rd_cfg = 0 > cs0_odt_wr_cfg = 1 > cs1_odt_rd_cfg = 0 > cs1_odt_wr_cfg = 1 > cs0_odt_rtt_norm = 3 > cs0_odt_rtt_wr = 0 > cs1_odt_rtt_norm = 0 > cs1_odt_rtt_wr = 0 > memctl_interleaving = 0 > memctl_interleaving_mode = 0 > ba_intlv_ctl = 0x00000040 > ECC_mode = 0 > ECC_init_using_memctl = 1 > DQS_config = 1 > self_refresh_in_sleep = 1 > dynamic_power = 0 > data_bus_width = 0 > burst_length = 6 > cas_latency_override = 0 > cas_latency_override_value = 3 > use_derated_caslat = 0 > additive_latency_override = 0 > additive_latency_override_value = 3 > clk_adjust = 6 > cpo_override = 31 > write_data_delay = 4 > half_strength_driver_enable = 0 > twoT_en = 0 > threeT_en = 0 > registered_dimm_en = 0 > ap_en = 1 > bstopre = 256 > wrlvl_override = 1 > wrlvl_sample = 10 > wrlvl_start = 8 > rcw_override = 0 > rcw_1 = 0 > rcw_2 = 0 > tCKE_clock_pulse_width_ps = 9000 > tFAW_window_four_activates_ps = 0 > trwt_override = 0 > trwt = 0 > > > Address Assignment: Controller=0 DIMM=0 > Don't have this functionality yet > > > Computed Register Values: Controller=0 > cs0_bnds = 0x0000007F > cs0_config = 0x80014400 > cs0_config_2 = 0x00000000 > cs1_bnds = 0x00000000 > cs1_config = 0x80014400 > cs1_config_2 = 0x00000000 > timing_cfg_3 = 0x000F0000 > timing_cfg_0 = 0x40110104 > timing_cfg_1 = 0x000F8246 > timing_cfg_2 = 0x0FA8D0C0 > ddr_sdram_cfg = 0xC7004000 > ddr_sdram_cfg_2 = 0x24401040 > ddr_sdram_mode = 0x00401021 > ddr_sdram_mode_2 = 0x00000000 > ddr_sdram_mode_3 = 0x00000000 > ddr_sdram_mode_4 = 0x00000000 > ddr_sdram_mode_5 = 0x00000000 > ddr_sdram_mode_6 = 0x00000000 > ddr_sdram_mode_7 = 0x00000000 > ddr_sdram_mode_8 = 0x00000000 > ddr_sdram_interval = 0x00000100 > ddr_data_init = 0xDEADBEEF > ddr_sdram_clk_cntl = 0x03000000 > ddr_init_addr = 0x00000000 > ddr_init_ext_addr = 0x00000000 > timing_cfg_4 = 0x00220001 > timing_cfg_5 = 0x1C401400 > ddr_zq_cntl = 0x89080600 > ddr_wrlvl_cntl = 0x8675A608 > ddr_sr_cntr = 0x00000000 > ddr_sdram_rcw_1 = 0x00000000 > ddr_sdram_rcw_2 = 0x00000000 > ddr_cdr1 = 0x00000000 > ddr_cdr2 = 0x00000000 > err_disable = 0x00000000 > err_int_en = 0x00000000 > debug_01 = 0x00000000 > debug_02 = 0x00000000 > debug_03 = 0x00000000 > debug_04 = 0x00000000 > debug_05 = 0x00000000 > debug_06 = 0x00000000 > debug_07 = 0x00000000 > debug_08 = 0x00000000 > debug_09 = 0x00000000 > debug_10 = 0x00000000 > debug_11 = 0x00000000 > debug_12 = 0x00000000 > debug_13 = 0x00000000 > debug_14 = 0x00000000 > debug_15 = 0x00000000 > debug_16 = 0x00000000 > debug_17 = 0x00000000 > debug_18 = 0x00000000 > debug_19 = 0x00000000 > debug_20 = 0x00000000 > debug_21 = 0x00000000 > debug_22 = 0x00000000 > debug_23 = 0x00000000 > debug_24 = 0x00000000 > debug_25 = 0x00000000 > debug_26 = 0x00000000 > debug_27 = 0x00000000 > debug_28 = 0x00000000 > debug_29 = 0x00000000 > debug_30 = 0x00000000 > debug_31 = 0x00000000 > debug_32 = 0x00000000 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
