On Jul 25, 2011, at 12:57 PM, Wolfgang Denk wrote: > Dear Kumar Gala, > > In message <aa4fd7c8-6be0-4847-9332-3ad9521c0...@kernel.crashing.org> you > wrote: >> >>> DRAM: __fsl_ddr_set_lawbar: ERROR (ctrl #0, intrlv=3D0) >>> 256 MiB (DDR1, 64-bit, CL=3D2, ECC off) > ... >> On this board what is 'reset' really doing? I have a theory but would >> be helpful to understand what's happening. > > This is a MPC8555 based board: > > CPU: 8555E, Version: 1.1, (0x80790011) > Core: Unknown, Version: 2.0, (0x80200020) > > THe do_reset() code is supposed to be the one from > "arch/powerpc/cpu/mpc85xx/cpu.c" > > Side note: rebooting Linux doesn't work either - it just hangs the > board in Linux v3.0 and any earlier version I can still compile with > my Fedora15 based host, i.e. down to around 2.6.32 or so. > >> Can you also send me the full boot log (i'm looking at another bug that >> might show up on this board). > > Will do as PM.
Do you know if this board has any real reset on a FPGA or CPLD or something like that. The problem on the 8555/8541 is the reset you are trigger is just a core reset and not one of the full SoC. If there is a board level means I would suggest trying to utilize it instead. If not this might be painful & problematic as you'll have to slowly make sure we are 'resetting' each SoC block properly. - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
