Dear Kumar, I'm seeing the following problem on a MPC8555 board:
Power-on reset works fine: ... I2C: ready DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Flash: 64 MiB L2: 256 KB enabled ... But a soft-reset results in this: => reset ... I2C: ready DRAM: __fsl_ddr_set_lawbar: ERROR (ctrl #0, intrlv=0) 256 MiB (DDR1, 64-bit, CL=2, ECC off) Flash: 64 MiB L2: 256 KB already enabled ... Do you have any idea what this means and how to fix it? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de In general, if you think something isn't in Perl, try it out, because it usually is :-) - Larry Wall in <1991jul31.174523.9...@netlabs.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
