On Jul 25, 2011, at 3:18 AM, Wolfgang Denk wrote: > Dear Kumar, > > I'm seeing the following problem on a MPC8555 board: > > Power-on reset works fine: > > ... > I2C: ready > DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off) > Flash: 64 MiB > L2: 256 KB enabled > ... > > But a soft-reset results in this: > > => reset > ... > I2C: ready > DRAM: __fsl_ddr_set_lawbar: ERROR (ctrl #0, intrlv=0) > 256 MiB (DDR1, 64-bit, CL=2, ECC off) > Flash: 64 MiB > L2: 256 KB already enabled > ... > > > Do you have any idea what this means and how to fix it?
On this board what is 'reset' really doing? I have a theory but would be helpful to understand what's happening. Can you also send me the full boot log (i'm looking at another bug that might show up on this board). - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
