On 5/12/25 8:42 PM, Cody Eksal wrote:
> On 2025/05/10 10:09 pm, Andre Przywara wrote:
>> From: Cody Eksal <masterr3c0rd@epochal.quest>
>>
>> This adds preliminary support for the DRAM controller in the Allwinner
>> A100/A133 SoCs.
>> This is work in progress, and has rough edges, but works on at least
>> three different boards. It contains support for DDR4 and LPDDR4.
>>
>> [Andre: formatting fixes, adapt to mainline, drop unused parameters,
>> remove struct struct sunxi_mctl_com_reg, hardcode MR registers,
>> switch to mctl_check_pattern(), remove simple DRAM check]
>
> Thank you Andre for cleaning up my patches. Life has a nasty way of
> getting in the way when it's least convenient.
>
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Thanks Andre and Cody for the cleanup and work here. I tried booting
this on my A133 helper board with 1GB RAM and it worked fine. I have
a custom PCB with 4GB which fails to boot fully. I have added the
log and defconfig below.
I have added additional debug in the u-boot booting, i.e SPL booted
and u-boot as well (after BL31), but failed to resume from the relocated
address.
Previous version i.e 2024.10.x tree from Cody boots fine, but when I
was able to work only upto 1GB address, accessing beyond that crashes
in the kernel boot flow.
Did I miss some configuration?
vendor u-boot DRAM related snippet from console:
[759]dram_para[0]:0x318
[761]dram_para[1]:0x8
[763]dram_para[2]:0x7070707
[766]dram_para[3]:0xd0d0d0d
[769]dram_para[4]:0xe0e
[771]dram_para[5]:0xd0a050c
[774]dram_para[6]:0x310a
[777]dram_para[7]:0x10001000
[779]dram_para[8]:0x0
[782]dram_para[9]:0x34
[784]dram_para[10]:0x1b
[786]dram_para[11]:0x33
[789]dram_para[12]:0x3
[791]dram_para[13]:0x0
[793]dram_para[14]:0x0
[795]dram_para[15]:0x4
[798]dram_para[16]:0x72
[800]dram_para[17]:0x0
[802]dram_para[18]:0x7
[805]dram_para[19]:0x0
[807]dram_para[20]:0x0
[809]dram_para[21]:0x26
[812]dram_para[22]:0x6060606
[815]dram_para[23]:0x84040404
[818]dram_para[24]:0x0
[820]dram_para[25]:0x0
[822]dram_para[26]:0x48010101
[825]dram_para[27]:0x273333
[828]dram_para[28]:0x1e19131c
[831]dram_para[29]:0x14141312
[834]dram_para[30]:0x7521
[836]dram_para[31]:0x2023211f
[844]DRAM BOOT DRIVE INFO: V0.69
[863]DRAM_VCC set to 1100 mv
[866]DRAM CLK =792 MHZ
[868]DRAM Type =8 (3:DDR3,4:DDR4,7:LPDDR3,8:LPDDR4)
[878]DRAM SIZE =4096 MBytes, para1 = 310a, para2 = 10001000, tpr13 = 7521
[890]DRAM simple test OK.
[893]dram size =4096
Upstream defconfig used:
CONFIG_DRAM_SUNXI_DX_ODT=0x7070707
CONFIG_DRAM_SUNXI_DX_DRI=0xd0d0d0d
CONFIG_DRAM_SUNXI_CA_DRI=0xe0e
CONFIG_DRAM_SUNXI_PARA0=0xd0a050c
CONFIG_DRAM_SUNXI_MR11=0x4
CONFIG_DRAM_SUNXI_MR12=0x72
CONFIG_DRAM_SUNXI_MR14=0x7
CONFIG_DRAM_SUNXI_TPR1=0x26
CONFIG_DRAM_SUNXI_TPR2=0x6060606
CONFIG_DRAM_SUNXI_TPR3=0x84040404
CONFIG_DRAM_SUNXI_TPR6=0x48010101
CONFIG_DRAM_SUNXI_TPR10=0x273333
CONFIG_DRAM_SUNXI_TPR11=0x1e19131c
CONFIG_DRAM_SUNXI_TPR12=0x14141312
CONFIG_DRAM_SUNXI_TPR13=0x7521
CONFIG_DRAM_SUNXI_TPR14=0x2023211f
CONFIG_MACH_SUN50I_A133=y
CONFIG_SUNXI_DRAM_A133_LPDDR4=y
CONFIG_DRAM_CLK=792
Upstream boot log:
U-Boot SPL 2025.07-rc2-00008-g9dab0d385a9d (May 26 2025 - 19:06:29 +0530)
[1/37737]
DRAM: 4096 MiB
Trying to boot from FEL
NOTICE: BL31: v2.12.0(debug):v2.13-rc1-3-g35e7dd0a6-dirty
NOTICE: BL31: Built : 20:27:56, May 22 2025
NOTICE: BL31: Detected Allwinner A100/A133 SoC (1855)
NOTICE: BL31: Found U-Boot DTB at 0xa0a2e80, model: MEC electronics A133 DM2
INFO: ARM GICv2 driver initialized
INFO: Configuring SPC Controller
INFO: Probing for PMIC on I2C
INFO: PMIC: found AXP717
INFO: BL31: Platform setup done
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for erratum 855873 was applied
INFO: BL31: cortex_a53: CPU workaround for erratum 1530924 was applied
INFO: PSCI: Suspend is unavailable
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x4a000000
INFO: SPSR = 0x3c9
initcall_run_f 899
U-Boot 2025.07-rc2-00008-g9dab0d385a9d (May 26 2025 - 19:06:29 +0530) Allwinner
Technology
U-Boot code: 4A000000 -> 4A094C48 BSS: -> 4A09EE70
CPU: Allwinner A133 (SUN50I)
Model: MEC electronics A133 DM2
initcall_run_f 960
DRAM: initcall_run_f 963
initcall_run_f 968
Monitor len: 0009ee70
Ram size: 100000000
Ram top: 100000000
initcall_run_f 990
initcall_run_f 998
Reserving 635k for U-Boot at: fff51000
initcall_run_f 1005
Reserving 65664k for malloc() at: fbf31000
Reserving 120 Bytes for Board Info at: fbf30f80
Reserving 368 Bytes for Global Data at: fbf30e10
Reserving 19968 Bytes for FDT at: fbf2c010
initcall_run_f 1015
initcall_run_f 1020
initcall_run_f 1022
RAM Configuration:
Bank #0: 40000000 4 GiB
DRAM: 4 GiB
initcall_run_f 1024
initcall_run_f 1026
New Stack Pointer is: fbf2c000
Relocation Offset is: b5f51000
Relocating to fff51000, new gd at fbf30e10, sp at fbf2c000
initcall_run_f 1055
Thanks,
Parthiban
>
> - Cody
>
>> ---
>> .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 4 +
>> arch/arm/include/asm/arch-sunxi/dram.h | 2 +
>> .../include/asm/arch-sunxi/dram_sun50i_a133.h | 230 ++++
>> arch/arm/mach-sunxi/Kconfig | 104 +-
>> arch/arm/mach-sunxi/Makefile | 2 +
>> arch/arm/mach-sunxi/dram_sun50i_a133.c | 1204 +++++++++++++++++
>> arch/arm/mach-sunxi/dram_timings/Makefile | 2 +
>> arch/arm/mach-sunxi/dram_timings/a133_ddr4.c | 80 ++
>> .../arm/mach-sunxi/dram_timings/a133_lpddr4.c | 102 ++
>> 9 files changed, 1722 insertions(+), 8 deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
>> create mode 100644 arch/arm/mach-sunxi/dram_sun50i_a133.c
>> create mode 100644 arch/arm/mach-sunxi/dram_timings/a133_ddr4.c
>> create mode 100644 arch/arm/mach-sunxi/dram_timings/a133_lpddr4.c
>>
>
