On Mon, 12 May 2025 11:21:33 +0200 Quentin Schulz <quentin.sch...@cherry.de> wrote:
> Hi Andre, > > On 5/11/25 3:09 AM, Andre Przywara wrote: > > From: Cody Eksal <masterr3c0rd@epochal.quest> > > > > This adds preliminary support for the DRAM controller in the Allwinner > > A100/A133 SoCs. > > This is work in progress, and has rough edges, but works on at least > > three different boards. It contains support for DDR4 and LPDDR4. > > > > [Andre: formatting fixes, adapt to mainline, drop unused parameters, > > remove struct struct sunxi_mctl_com_reg, hardcode MR registers, > > switch to mctl_check_pattern(), remove simple DRAM check] > > Missing Cody's and your Signed-off-by. Yeah, I know, I am hoping for Cody to reply to this mail with the line, since it was also missing in his github, and I don't think I can just slap SoB lines on someone's patches. I will add mine then as well. Thanks, Andre
