On 2025/05/10 10:09 pm, Andre Przywara wrote:
From: Cody Eksal <masterr3c0rd@epochal.quest>This adds preliminary support for the DRAM controller in the Allwinner A100/A133 SoCs. This is work in progress, and has rough edges, but works on at least three different boards. It contains support for DDR4 and LPDDR4. [Andre: formatting fixes, adapt to mainline, drop unused parameters, remove struct struct sunxi_mctl_com_reg, hardcode MR registers, switch to mctl_check_pattern(), remove simple DRAM check]
Thank you Andre for cleaning up my patches. Life has a nasty way of getting in the way when it's least convenient. Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest> - Cody
--- .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 4 + arch/arm/include/asm/arch-sunxi/dram.h | 2 + .../include/asm/arch-sunxi/dram_sun50i_a133.h | 230 ++++ arch/arm/mach-sunxi/Kconfig | 104 +- arch/arm/mach-sunxi/Makefile | 2 + arch/arm/mach-sunxi/dram_sun50i_a133.c | 1204 +++++++++++++++++ arch/arm/mach-sunxi/dram_timings/Makefile | 2 + arch/arm/mach-sunxi/dram_timings/a133_ddr4.c | 80 ++ .../arm/mach-sunxi/dram_timings/a133_lpddr4.c | 102 ++ 9 files changed, 1722 insertions(+), 8 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h create mode 100644 arch/arm/mach-sunxi/dram_sun50i_a133.c create mode 100644 arch/arm/mach-sunxi/dram_timings/a133_ddr4.c create mode 100644 arch/arm/mach-sunxi/dram_timings/a133_lpddr4.c
