High Speed enable bit switches data launch from the falling
clock edge (half cycle timing) to the rising clock edge (full
cycle timing). For all SD UHS modes, data launch must happen
at the rising clock edge, so set HIGH_SPEED_ENA for SDR12 and
SDR25 modes. For all HS modes, data launch must happen at the
falling clock edge, so do not set HIGH_SPEED_ENA for MMC_HS_52.
Signed-off-by: Judith Mendez <j...@ti.com>
---
drivers/mmc/am654_sdhci.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index e4fa8a88565..28d82afd012 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -412,8 +412,7 @@ static void am654_sdhci_write_b(struct sdhci_host *host, u8
val, int reg)
*/
case SD_HS:
case MMC_HS:
- case UHS_SDR12:
- case UHS_SDR25:
+ case MMC_HS_52:
val &= ~SDHCI_CTRL_HISPD;
default:
break;
--
2.49.0
