Hi Simon,
On 2025-02-09 22:14, Simon Glass wrote:
> The SPL phase has a single SPL binary plus a devicetree for each board
> we need to support.
>
> The devicetree is run through fdtgrep to remove unwanted nodes and
> properties and reduce its size.
>
> While it would be nicer to just have a single FIT holding both the SPL
> and U-Boot images, there may not be enough SRAM to support that. So we
> end up providing this special image just for SPL.
>
> Signed-off-by: Simon Glass <s...@chromium.org>
> ---
>
> (no changes since v1)
>
> arch/arm/dts/rockchip-u-boot.dtsi | 43 +++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
> b/arch/arm/dts/rockchip-u-boot.dtsi
> index c2a795957fb..9525cb9c21a 100644
> --- a/arch/arm/dts/rockchip-u-boot.dtsi
> +++ b/arch/arm/dts/rockchip-u-boot.dtsi
> @@ -153,6 +153,49 @@
> };
> };
> };
> +
> + spl_template: template-2 {
> + type = "fit";
> + description = "FIT image for U-Boot SPL";
> + #address-cells = <1>;
> + fit,fdt-list = "of-list";
> + fit,align = <512>;
> + fit,external-offset = <0>;
> + images {
> + spl {
> + description = "U-Boot SPL";
> + type = "firmware";
> + os = "u-boot";
> + arch = ARCH;
> + compression = "lz4";
> + load = <CONFIG_SPL_TEXT_BASE>;
> + entry = <CONFIG_SPL_TEXT_BASE>;
> + section {
> + compress = "lz4";
> + u-boot-spl-nodtb {
> + };
> + u-boot-spl-bss-pad {
> + };
> + };
> + };
> + @fdt-SEQ {
> + description = "fdt-NAME";
> + compression = "none";
> + type = "flat_dt";
> + fit,fdt-phase = "spl";
> + };
> + };
> + configurations {
> + default = "@config-DEFAULT-SEQ";
> + @config-SEQ {
> + description = "NAME.dtb";
> + fdt = "fdt-SEQ";
> + fit,firmware = "spl";
> + fit,loadables;
> + fit,compatible;
> + };
> + };
> + };
This template look very specific to VBE/VPL and can probably also be
moved to rockchip-vpl-u-boot.dtsi. Else this could need a comment on
e.g. why this does not use COMP as compression algo.
Regards,
Jonas
> #endif /* HAS_FIT */
>
> simple-bin {
