The TPL image must be built for each board we need to support. It is the
only part of the image which is board-specific.
This helps to save space and reduce the size of TPL, so that it can fit
within the internal 192K IRAM of the RK3399 SoC.
As with other phases, the TPL devicetree is run through fdtgrep to
remove unwanted nodes and properties and reduce its size.
Signed-off-by: Simon Glass <s...@chromium.org>
---
Changes in v2:
- Mention RK3399 with respect to the memory limit
- Move VPL things into a separate file
arch/arm/dts/rockchip-u-boot.dtsi | 4 +++-
arch/arm/dts/rockchip-vpl-u-boot.dtsi | 16 ++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 9525cb9c21a..0d59aad86bf 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -202,6 +202,7 @@
filename = "u-boot-rockchip.bin";
pad-byte = <0xff>;
+#ifndef CONFIG_VPL
mkimage {
filename = "idbloader.img";
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
@@ -227,7 +228,8 @@
u-boot-img {
offset = <CONFIG_SPL_PAD_TO>;
};
-#endif
+#endif /* HAS_FIT */
+#endif /* VPL */
fdtmap {
};
};
diff --git a/arch/arm/dts/rockchip-vpl-u-boot.dtsi
b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
index a02f44d27d2..621161f6c86 100644
--- a/arch/arm/dts/rockchip-vpl-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
@@ -59,6 +59,22 @@
};
simple-bin {
+ alternates-fdt {
+ fdt-list-dir = "dts/upstream/src/arm64/rockchip";
+ filename-pattern = "alt-NAME.bin";
+ fdt-phase = "tpl";
+
+ mkimage {
+ filename = "idbloader.img";
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ multiple-data-files;
+
+ u-boot-tpl {
+ symbols-base = <0>;
+ };
+ };
+ };
+
vpl {
type = "fit";
offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
0x200 + 0x8000)>;
--
2.43.0
