On Thu, Dec 7, 2023 at 2:51 PM Marek Vasut <ma...@denx.de> wrote: > > Import DRAM timings generated by the DDR tool 3.31 which introduce assorted > tweaks to the DRAM controller settings. Furthermore, enable DBI to improve > noise resilience of the DRAM bus by reducing the number of bit changes on > the bus. > > Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors > reported by EDAC . It is not entirely clear why the slightly faster setting > does produce sporadic correctable errors, while this one does not, but this > could be related to simpler PLL setting at 3600 MTps. > > Enable inline ECC which is necessary to detect ECC errors and collect > statistics by the EDAC driver in Linux. This reduces the DRAM size by > 64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available > DRAM size becomes 3.5 GiB . > > Signed-off-by: Marek Vasut <ma...@denx.de>
Reviewed-by: Fabio Estevam <feste...@gmail.com>
