On Fri, Jul 07, 2023 at 06:50:09PM +0800, Hal Feng wrote: > From: Xingyu Wu <xingyu...@starfivetech.com> > > Change the PLL clock source from syscrg to sys_syscon child node. > > Signed-off-by: Xingyu Wu <xingyu...@starfivetech.com> > Signed-off-by: Hal Feng <hal.f...@starfivetech.com> > --- > arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 +++--- > arch/riscv/dts/jh7110-u-boot.dtsi | 1 - > arch/riscv/dts/jh7110.dtsi | 8 ++++++-- > 3 files changed, 9 insertions(+), 6 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com>
