[PATCH v1 2/5] riscv: dts: jh7110: Add PLL clock controller node

[Hal Feng]

From: Xingyu Wu <xingyu...@starfivetech.com>

Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu <xingyu...@starfivetech.com>
Signed-off-by: Hal Feng <hal.f...@starfivetech.com>
---
 arch/riscv/dts/jh7110.dtsi | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..3e5bddccc5 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -491,8 +491,14 @@
                };
 
                sys_syscon: sys_syscon@13030000 {
-                       compatible = "starfive,jh7110-sys-syscon","syscon";
+                       compatible = "starfive,jh7110-sys-syscon","syscon", 
"simple-mfd";
                        reg = <0x0 0x13030000 0x0 0x1000>;
+
+                       pllclk: clock-controller {
+                               compatible = "starfive,jh7110-pll";
+                               clocks = <&osc>;
+                               #clock-cells = <1>;
+                       };
                };
 
                sysgpio: pinctrl@13040000 {
-- 
2.38.1