On Tue, 11 Jul 2023 11:09:23 +0200, Torsten Duwe wrote: > On Fri, 7 Jul 2023 18:50:06 +0800 > Hal Feng <hal.f...@starfivetech.com> wrote: > >> The clock dt-bindings and DT nodes are not consistent with Linux now. >> Let's sync them with Linux, so the same dtb can work for Linux & U-Boot. >> >> To achieve this goal, the PLL clock driver is separated and some clock >> IDs conversion is needed in clock drivers. >> >> For the motivation, please see the discussion in the link below. >> >> [1] >> https://patchwork.kernel.org/project/linux-riscv/patch/20230512022036.97987-2-xingyu...@starfivetech.com/ >> >> Xingyu Wu (5): >> clk: starfive: jh7110: Separate the PLL driver >> riscv: dts: jh7110: Add PLL clock controller node >> riscv: dts: jh7110: Add clock source from PLL >> dt-bindings: clock: jh7110: Modify clock id to be same with Linux >> clk: starfive: jh7110: Add of_xlate ops and macros for clock id >> conversion > > For better bisectability, I would have put patch 2 first, then merged 1&3, > then merged 4&5. This way U-Boot should compile and boot after each patch > (I think, untested ;) But given the rapid development of the platform,
Yes, it will get better bisectability if we do so, but it is not a good coding style as we merge the driver changes and the DT changes in one patch. Does someone else have any suggestions? > I'm fine with inclusion of the series as-is; as it does not affect other > targets. > > I'm also wondering whether the symbolic clock number constants should be > synced, too. But that's also a minor issue, as long as they expand to yield > the same numbers. Good catch. The main difference is the definitions of PLL and STG. You can simply compare them with the definitions in linux [1] in the link below. [1] https://github.com/starfive-tech/linux/blob/JH7110_VisionFive2_upstream/include/dt-bindings/clock/starfive%2Cjh7110-crg.h I will sync them in the next version. > > For the series: > > Reviewed-by: Torsten Duwe <d...@suse.de> Thanks for your review. Best regards, Hal
