Hi Wolfgang,
On Fri, Jun 18, 2010 at 4:03 PM, Wolfgang Denk <w...@denx.de> wrote:
> diff --git a/arch/arm/cpu/arm_cortexa8/omap3/cache.S
> b/arch/arm/cpu/arm_cortexa8/omap3/cache.S
> index 0f63815..4b65ac5 100644
> --- a/arch/arm/cpu/arm_cortexa8/omap3/cache.S
> +++ b/arch/arm/cpu/arm_cortexa8/omap3/cache.S
> @@ -130,7 +130,7 @@ finished_inval:
>
>
> l2_cache_enable:
> - push {r0, r1, r2, lr}
> + stmfd r13!, {r0, r1, r2, lr}
> @ ES2 onwards we can disable/enable L2 ourselves
> bl get_cpu_rev
> cmp r0, #CPU_3XX_ES20
> @@ -157,11 +157,11 @@ l2_cache_enable_EARLIER_THAN_ES2:
> mov ip, r3
> str r3, [sp, #4]
> l2_cache_enable_END:
> - pop {r1, r2, r3, pc}
> + ldmfd r13!, {r1, r2, r3, pc}
For clarity's sake, it might be worth using sp instead of r13
Cheers,
Albin
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