The push / pop instructions used in this file are available only with
more recent tool chains:
cache.S: Assembler messages:
cache.S:133: Error: bad instruction `push {r0,r1,r2,lr}'
cache.S:160: Error: bad instruction `pop {r1,r2,r3,pc}'
cache.S:164: Error: bad instruction `push {r0,r1,r2,lr}'
cache.S:191: Error: bad instruction `pop {r1,r2,r3,pc}'
Change push/pop into stmfd/ldmfd instructions to support older
versions of binutils as well.
I verified that the modified source code generates exactly the same
binary code.
Signed-off-by: Wolfgang Denk <w...@denx.de>
Cc: Sandeep Paulraj <s-paul...@ti.com>
Cc: Tom Rix <t...@bumblecow.com>
---
arch/arm/cpu/arm_cortexa8/omap3/cache.S | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/cache.S
b/arch/arm/cpu/arm_cortexa8/omap3/cache.S
index 0f63815..4b65ac5 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/cache.S
+++ b/arch/arm/cpu/arm_cortexa8/omap3/cache.S
@@ -130,7 +130,7 @@ finished_inval:
l2_cache_enable:
- push {r0, r1, r2, lr}
+ stmfd r13!, {r0, r1, r2, lr}
@ ES2 onwards we can disable/enable L2 ourselves
bl get_cpu_rev
cmp r0, #CPU_3XX_ES20
@@ -157,11 +157,11 @@ l2_cache_enable_EARLIER_THAN_ES2:
mov ip, r3
str r3, [sp, #4]
l2_cache_enable_END:
- pop {r1, r2, r3, pc}
+ ldmfd r13!, {r1, r2, r3, pc}
l2_cache_disable:
- push {r0, r1, r2, lr}
+ stmfd r13!, {r0, r1, r2, lr}
@ ES2 onwards we can disable/enable L2 ourselves
bl get_cpu_rev
cmp r0, #CPU_3XX_ES20
@@ -188,4 +188,4 @@ l2_cache_disable_EARLIER_THAN_ES2:
mov ip, r3
str r3, [sp, #4]
l2_cache_disable_END:
- pop {r1, r2, r3, pc}
+ ldmfd r13!, {r1, r2, r3, pc}
--
1.7.0.1
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